Philips HEF4017BPB, HEF4017BP, HEF4017BDB, HEF4017BD, HEF4017BU Datasheet

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DATA SH EET
Product specification File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4017B MSI
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
5-stage Johnson counter
HEF4017B
MSI
DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Ooto O9), an active LOW output from the most significant flip-flop (O
5-9
), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).
The counter is advanced by either a LOW to HIGH transition at CP0while CP1is LOW or a HIGH to LOW transition at CP1while CP0is HIGH (see also function table).
When cascading counters, the
O
5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0input of the next counter.
A HIGH on MR resets the counter to zero (O
o
= O
5-9
= HIGH; O1to O9= LOW) independent of the
clock inputs (CP0, CP1). Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4017BP(N): 16-lead DIL; plastic (SOT38-1) HEF4017BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4017BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
CP
0
clock input (LOW to HIGH triggered)
CP
1
clock input (HIGH to LOW triggered) MR master reset input O
0
to O
9
decoded outputs O
5-9
carry output (active LOW)
January 1995 3
Philips Semiconductors Product specification
5-stage Johnson counter
HEF4017B
MSI
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Fig.3 Logic diagram.
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