Philips hef4017b DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4017B
MSI
5-stage Johnson counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
5-stage Johnson counter
DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (Ooto O9), an
active LOW output from the most significant flip-flop (O
active HIGH and active LOW clock inputs (CP0, CP1) and
an overriding asynchronous master reset input (MR).
The counter is advanced by either a LOW to HIGH
transition at CP0while CP1is LOW or a HIGH to LOW
transition at CP1while CP0is HIGH (see also function
table).
O
When cascading counters, the
output, which is LOW
5-9
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0input of the next counter.
5-9
HEF4017B
A HIGH on MR resets the counter to zero
= O
(O
o
clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an
),
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
= HIGH; O1to O9= LOW) independent of the
5-9
MSI
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4017BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4017BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4017BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
January 1995 2
PINNING
CP
CP
0
1
clock input (LOW to HIGH triggered)
clock input (HIGH to LOW triggered)
MR master reset input
O
to O
0
9
O
5-9
FAMILY DATA, I
decoded outputs
carry output (active LOW)
LIMITS category MSI
DD
See Family Specifications
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January 1995 3
Philips Semiconductors Product specification
5-stage Johnson counter
Fig.3 Logic diagram.
HEF4017B
MSI
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