Philips HEF40175BU, HEF40175BT, HEF40175BPB, HEF40175BP, HEF40175BDB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF40175B

MSI

Quadruple D-type flip-flop

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Quadruple D-type flip-flop

HEF40175B

MSI

DESCRIPTION

The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),

an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary

buffered outputs (O0 to O3). Information on D0 to D3 is transferred to O0 to O3 on the LOW to HIGH transition of

CP if MR is HIGH. When LOW, MR resets all flip-flops (O0 to O3 = LOW, O0 to O3 = HIGH), independent of CP and D0 to D3.

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

HEF40175BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF40175BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF40175BT(D): 16-lead SO; plastic

(SOT109-1)

PINNING
	D0 to D3					data inputs
	CP					clock input (LOW to HIGH; edge-triggered)
						master reset input (active LOW)
	MR
	O0 to O3					buffered outputs
					3	complementary buffered outputs
	O	0 to		O

FUNCTION TABLE

	INPUTS				OUTPUTS
CP	D				O
			MR				O
	H		H		H		L
	L		H		L		H
	X		H		no change	no change
X	X		L		L		H

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

Notes

1.H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial

= positive-going transition = negative-going transition

2