Philips HEF4016BU, HEF4016BT, HEF4016BPB, HEF4016BP, HEF4016BDB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4016B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4016B
gates
DESCRIPTION
The HEF4016B has four independent analogue switches
(transmission gates). Each switch has two input/output
terminals (Y/Z) and an active HIGH enable input (E). When
E is connected to VDDa low impedance bidirectional path
between Y and Z is established (ON condition). When E is
connected to VSSthe switch is disabled and a high
impedance between Y and Z is established (OFF
condition). Current through a switch will not cause
additional V
DD
current provided the voltage at the
terminals of the switch is maintained within the supply
voltage range; VDD≥ (VY, VZ) ≥ VSS. Inputs Y and Z are
electrically equivalent terminals.
Fig.1 Functional diagram.
HEF4016BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4016BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)
HEF4016BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4016B are:
• Signal gating
• Modulation
• Demodulation
• Chopper
E
0
to E
3
enable inputs
Y
0
to Y
3
input/output terminals
Z
0
to Z
3
input/output terminals
Fig.3 Schematic diagram
(one switch).
January 1995 3
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4016B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
T
amb
=25°C; VSS= 0 V (unless otherwise specified)
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
PARAMETER
V
DD
V
SYMBOL TYP. MAX. UNIT CONDITIONS
5 8000 −ΩE
n
at VIH; Vis= 0 to VDD; see Fig.4
ON resistance 10 R
ON
230 690 Ω
15 115 350 Ω
5 140 425 Ω Enat VIH; Vis=VSS; see Fig.4
ON resistance 10 R
ON
65 195 Ω
15 50 145 Ω
5 170 515 Ω Enat VIH; Vis=VDD; see Fig.4
ON resistance 10 R
ON
95 285 Ω
15 75 220 Ω
‘∆’ ON resistance 5 200 −ΩE
n
at VIH; Vis= 0 to VDD; see Fig.4
between any two 10 ∆R
ON
15 −Ω
channels 15 10 −Ω
PARAMETER
V
DD
V SYMBOL
T
amb
(°C)
UNIT−40 + 25 + 85 CONDITION
MIN. MAX. MIN. MAX. MIN. MAX.
Quiescent 5 − 1,0 − 1,0 − 7,5 µAV
SS
= 0; all valid
input combinations;
VI=VSSor V
DD
device 10 I
DD
− 2,0 − 2,0 − 15,0 µA
current 15 − 4,0 − 4,0 − 30,0 µA
Input leakage
15 ± I
IN
−−−300 − 1000
nA E
n
at VSSor V
DD
current at E
n
OFF-state leakage 5 −−−−−−nA Enat VIL;
Vis=VSSor VDD;
Vos=VDDor V
SS
current, any 10 I
OZ
−−−−−−nA
channel OFF 15 −−−200 −−nA
E
n
input 5 − 1,5 − 1,5 − 1,5 V switch OFF; see
Fig.9 for I
OZ
voltage LOW 10 V
IL
− 3,0 − 3,0 − 3,0 V
15 − 4,0 − 4,0 − 4,0 V
E
n
input 5 3,5 − 3,5 − 3,5 − V low-impedance
between Y and Z (ON
condition)
see RONswitch
voltage HIGH 10 V
IH
7,0 − 7,0 − 7,0 − V
15 11,0 − 11,0 − 11,0 − V
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