Philips hef40163b DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF40163B
MSI

4-bit synchronous binary counter
with synchronous reset

Product specification
File under Integrated Circuits, IC04

January 1995

Philips Semiconductors Product specification

4-bit synchronous binary counter with
synchronous reset

DESCRIPTION

The HEF40163B is a fully synchronous edge-triggered
4-bit binary counter with a clock input (CP), four
synchronous parallel data inputs (P0to P3), four
synchronous mode control inputs (parallel enable (PE),
count enable parallel (CEP), count enable trickle (CET)
and synchronous reset (SR)), buffered outputs from all
four bit positions (O0to O3) and a terminal count output
(TC).

Operation is fully synchronous and occurs on the LOW to
HIGH transition of CP. When
HIGH transition of CP loads data into the counter from
P0to P3. When PE is HIGH, the next LOW to HIGH

PE is LOW, the next LOW to

HEF40163B

MSI

transition of CP advances the counter to its next state only
if both CEP and CET are HIGH; otherwise no change
occurs in the state of the counter. TC is HIGH when the
state of the counter is 15 (O
CET is HIGH. A LOW on SR sets all outputs (O0to O3and
TC) LOW on the next LOW to HIGH transition of CP,
independent of the state of all other synchronous mode
control inputs (CEP, CET and PE). Multistage
synchronous counting is possible without additional
components by using a carry look-ahead counting
technique; in this case, TC is used to enable successive
cascaded stages. CEP, CET, PE and SR must be stable
only during the set-up time before the LOW to HIGH
transition of CP.

to O3= HIGH) and when

0

Fig.1 Functional diagram.

FAMILY DATA, I

See Family Specifications

January 1995 2

LIMITS category MSI

DD

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January 1995 3

Philips Semiconductors Product specification

4-bit synchronous binary counter with

synchronous reset

Fig.2 Logic diagram.

HEF40163B

MSI