Philips hef40161b DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF40161B
MSI

4-bit synchronous binary counter
with asynchronous reset

Product specification
File under Integrated Circuits, IC04

January 1995

Philips Semiconductors Product specification

4-bit synchronous binary counter with
asynchronous reset

DESCRIPTION

The HEF40161B is a fully synchronous edge-triggered
4-bit binary counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0to O3) and a terminal count output (TC).

Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0to P3regardless of the levels
of CEP and CET inputs.

HEF40161B

MSI

PE is HIGH, the next LOW to HIGH transition of CP

When
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
15 (O1to O3= HIGH) and when CET is HIGH. A LOW on
MR sets all outputs (O0to O3and TC) LOW, independent
of the state of all other inputs. Multistage synchronous
counting is possible without additional components by
using a carry look-ahead counting technique; in this case,
TC is used to enable successive cascaded stages. CEP,
CET and PE must be stable only during the set-up time
before the LOW to HIGH transition of CP.

Fig.1 Functional diagram.

FAMILY DATA, I

See Family Specifications

January 1995 2

LIMITS category MSI

DD

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January 1995 3

Philips Semiconductors Product specification

4-bit synchronous binary counter with

asynchronous reset

Fig.2 Logic diagram.

HEF40161B

MSI