Philips HEF4015BU, HEF4015BT, HEF4015BPB, HEF4015BDB, HEF4015BD Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4015B

MSI

Dual 4-bit static shift register

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Dual 4-bit static shift register

HEF4015B

MSI

DESCRIPTION

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information

Fig.1	Functional diagram.
PINNING
DA, DB	serial data input
MRA, MRB	master reset input (active HIGH)
CPA, CPB	clock input (LOW-to-HIGH
	edge-triggered)
O0A, O1A, O2A, O3A	parallel outputs
O0B, O1B, O2B, O3B	parallel outputs

APPLICATION INFORMATION

Some examples of applications for the HEF4015B are:

∙Serial-to-parallel converter

∙Buffer stores

∙General purpose register

present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the register and forces O0 to O3 to LOW, independent of CP and D. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Fig.2 Pinning diagram.

HEF4015BP(N):	16-lead DIL; plastic
	(SOT38-1)
HEF4015BD(F):	16-lead DIL; ceramic (cerdip)
	(SOT74)
HEF4015BT(D):	16-lead SO; plastic
	(SOT109-1)

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

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