Philips HEF4007UBU, HEF4007UBT, HEF4007UBPB, HEF4007UBP, HEF4007UBDB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4007UB gates
Dual complementary pair and inverter
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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Dual complementary pair and inverter
HEF4007UB gates
DESCRIPTION
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode MOS transistors.
Fig.1 Schematic diagram.
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PINNING |
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SP2, SP3 |
source connections to 2nd and 3rd |
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p-channel transistors |
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DP1, DP2 |
drain connections from the 1st and 2nd |
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p-channel transistors |
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DN1, DN2 |
drain connections from the 1st and 2nd |
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n-channel transistors |
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SN2, SN3 |
source connections to the 2nd and 3rd |
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Fig.2 Pinning diagram. |
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n-channel transistors |
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DN/P3 |
common connection to the 3rd p-channel |
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and n-channel transistor drains |
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HEF4007UBP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4007UBD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4007UBT(D): 14-lead SO; plastic
(SOT108-1)
G1 to G3 gate connections to n-channel and p-channel of the three transistor pairs
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications for VIH/VIL unbuffered stages
( ): Package Designator North America
January 1995 |
2 |
Philips Semiconductors Product specification
Dual complementary pair and inverter |
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HEF4007UB |
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gates |
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AC CHARACTERISTICS |
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VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times £ 20 ns |
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VDD |
SYMBOL |
TYP. |
MAX. |
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TYPICAL EXTRAPOLATION |
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V |
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FORMULA |
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Propagation delays |
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Gn ® DN ; DP |
5 |
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40 |
80 |
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13 ns + (0,55 ns/pF) CL |
HIGH to LOW |
10 |
tPHL |
20 |
40 |
ns |
9 ns + (0,23 ns/pF) CL |
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15 |
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15 |
30 |
ns |
7 ns + (0,16 ns/pF) CL |
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5 |
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40 |
75 |
ns |
13 ns + (0,55 ns/pF) CL |
LOW to HIGH |
10 |
tPLH |
20 |
40 |
ns |
9 ns + (0,23 ns/pF) CL |
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15 |
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15 |
30 |
ns |
7 ns + (0,16 ns/pF) CL |
Output transition times |
5 |
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60 |
120 |
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10 ns + (1,0 ns/pF) CL |
HIGH to LOW |
10 |
tTHL |
30 |
60 |
ns |
9 ns + (0,42 ns/pF) CL |
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15 |
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20 |
40 |
ns |
6 ns + (0,28 ns/pF) CL |
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5 |
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60 |
120 |
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10 ns + (1,0 ns/pF) CL |
LOW to HIGH |
10 |
tTLH |
30 |
60 |
ns |
9 ns + (0,42 ns/pF) CL |
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15 |
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20 |
40 |
ns |
6 ns + (0,28 ns/pF) CL |
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VDD |
TYPICAL FORMULA FOR P (mW) |
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V |
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Dynamic power |
5 |
4500 fi + å (foCL) ´ VDD2 |
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where |
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dissipation per |
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20 000 fi + å (foCL) ´ VDD2 |
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fi = input freq. (MHz) |
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package (P) |
15 |
50 000 fi + å (foCL) ´ VDD2 |
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fo = output freq. (MHz) |
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CL = load capacitance (pF) |
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å(foCL) = sum of outputs |
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VDD = supply voltage (V) |
January 1995 |
3 |
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