Philips HEF4007UBU, HEF4007UBT, HEF4007UBPB, HEF4007UBP, HEF4007UBDB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4007UB
gates
Dual complementary pair and
inverter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Dual complementary pair and inverter
HEF4007UB
gates
DESCRIPTION
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and
three p-channel enhancement mode MOS transistors.
Fig.1 Schematic diagram.
HEF4007UBP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4007UBD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4007UBT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications for V
IH/VIL
unbuffered stages
S
P2
, S
P3
source connections to 2nd and 3rd
p-channel transistors
D
P1
, D
P2
drain connections from the 1st and 2nd
p-channel transistors
D
N1,DN2
drain connections from the 1st and 2nd
n-channel transistors
S
N2,SN3
source connections to the 2nd and 3rd
n-channel transistors
D
N/P3
common connection to the 3rd p-channel
and n-channel transistor drains
G
1
to G3gate connections to n-channel and
p-channel of the three transistor pairs
January 1995 3
Philips Semiconductors Product specification
Dual complementary pair and inverter
HEF4007UB
gates
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
=25°C; CL= 50 pF; input transition times ≤ 20 ns
V
DD
V
SYMBOL TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
Gn→ DN; D
P
5 40 80 ns 13 ns + (0,55 ns/pF) C
L
HIGH to LOW 10 t
PHL
20 40 ns 9 ns + (0,23 ns/pF) C
L
15 15 30 ns 7 ns + (0,16 ns/pF) C
L
5 40 75 ns 13 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
20 40 ns 9 ns + (0,23 ns/pF) C
L
15 15 30 ns 7 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 4500 f
i
+∑(foCL) × V
DD
2
where
dissipation per 10 20 000 f
i
+∑(foCL) × V
DD
2
fi= input freq. (MHz)
package (P) 15 50 000 f
i
+∑(foCL) × V
DD
2
fo= output freq. (MHz)
C
L
= load capacitance (pF)
∑(f
oCL
) = sum of outputs
V
DD
= supply voltage (V)
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