Philips hef4001ub DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4001UB
gates
Quadruple 2-input NOR gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
Quadruple 2-input NOR gate
DESCRIPTION
The HEF4001UB is a quadruple 2-input NOR gate. This
unbuffered single stage version provides a direct
implementation of the NOR function. The output
impedance and output transition time depends on the input
voltage and input rise and fall times applied.
HEF4001UB
gates
Fig.2 Pinning diagram.
HEF4001UBP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4001UBD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4001UBT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.3 Schematic diagram (one gate). The
splitting-up of the p-transistors provide
identical inputs.
FAMILY DATA, IDDLIMITS category GATES
See Family Specifications for V
unbuffered stages
IH/VIL
January 1995 2
Philips Semiconductors Product specification
Quadruple 2-input NOR gate
HEF4001UB
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays
In→ O
HIGH to LOW 10 t
LOW to HIGH 10 t
Output transition times 5 75 150 ns 15 ns + (1,20 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
Input capacitance C
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
5 65 130 ns 30 ns + (0,70 ns/pF) C
SYMBOL TYP. MAX.
PHL
15 25 50 ns 15 ns + (0,20 ns/pF) C
5 40 80 ns 13 ns + (0,55 ns/pF) C
PLH
15 15 30 ns 7 ns + (0,16 ns/pF) C
THL
15 20 40 ns 4 ns + (0,32 ns/pF) C
5 60 110 ns 10 ns + (1,00 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
IN
TYPICAL EXTRAPOLATION
FORMULA
30 60 ns 17 ns + (0,27 ns/pF) C
20 40 ns 9 ns + (0,23 ns/pF) C
30 60 ns 6 ns + (0,48 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
− 10 pF
gates
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 500 f
dissipation per 10 5000 f
package (P) 15 30 000 f
+ ∑ (foCL) × V
i
+ ∑ (foCL) × V
i
+ ∑ (foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
= load capacitance (pF)
C
L
∑(f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
January 1995 3
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