Philips HEF4104BU, HEF4104BT, HEF4104BPB, HEF4104BP, HEF4104BDB Datasheet
...
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4104B
MSI
Quadruple low to high voltage
translator with 3-state outputs
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Quadruple low to high voltage translator
with 3-state outputs
HEF4104B
MSI
DESCRIPTION
The HEF4104B quadruple low voltage to high voltage
translator with 3-state outputs provides the capability of
interfacing low voltage circuits to high voltage circuits,
such as low voltage LOCMOS and TTL to high voltage
LOCMOS. It has four data inputs (I0to I3), an active HIGH
output enable input (EO), four data outputs (O0to O3) and
their complements (O0to O3).
With EO HIGH, O0to O3and O0to O3are in the low
impedance ON-state, either HIGH or LOW as determined
by I
0
to I3; with EO LOW, O0to O3and O0to O3are in the
high impedance OFF-state.
The device uses a common negative supply (V
SS
) and
separate positive supplies for inputs (V
DDI
) and outputs
(V
DD0
). V
DDI
must always be less than or equal to V
DDO
,
even during power turn-on and turn-off. For the
permissible operating range of V
DDI
and V
DDO
see graph
Fig.4.
Each input protection circuit is terminated between
V
DDO
and VSS. This allows the input signals to be driven
from any potential between V
DDO
and VSS, without regard
to current limiting. When driving from potentials greater
than V
DDO
or less than VSS, the current at each input must
be limited to 10 mA.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4104BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4104BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4104BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
I
0
to I
3
data inputs
EO output enable input
O
0
to O
3
data outputs
O0to O
3
complementary data outputs
Fig.2 Pinning diagram.
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