Philips HCMOS Technical data

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INTEGRATED CIRCUITS

DATA SH EET

FAMILY SPECIFICATIONS

HCMOS family characteristics

File under Integrated Circuits, IC06

March 1988

Philips Semiconductors

HCMOS family characteristics

GENERAL

These family specifications cover the common electrical ratings and characteristics of the entire HCMOS 74HC/HCT/HCU family, unless otherwise specified in the individual device data sheet.

INTRODUCTION

The 74HC/HCT/HCU high-speed Si-gate CMOS logic family combines the low power advantages of the HE4000B family with the high speed and drive capability of the low power Schottky TTL (LSTTL).

The family will have the same pin-out as the 74 series and provide the same circuit functions.

In these families are included several HE4000B family circuits which do not have TTL counterparts, and some special circuits.

The basic family of buffered devices, designated as XX74HCXXXXX, will operate at CMOS input logic levels for high noise immunity, negligible typical quiescent supply and input current. It is operated from a power supply of 2to6V.

FAMILY

SPECIFICATIONS

A subset of the family, designated as XX74HCTXXXXX, with the same features and functions as the “HC-types”, will operate at standard TTL power supply voltage (5 V ± 10%) and logic input levels (0.8 to 2.0 V) for use as pin-to-pin compatible CMOS replacements to reduce power consumption without loss of speed. These types are also suitable for converted switching from TTL to CMOS.

Another subset, the XX74HCUXXXXX, consists of single-stage unbuffered CMOS compatible devices for application in RC or crystal controlled oscillators and other types of feedback circuits which operate in the linear mode.

HANDLING MOS DEVICES

Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling situations. However, to be totally safe, it is desirable to take handling precautions into account (see also

“HANDLING PRECAUTIONS”

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

74HC 74HCT

SYMBOL PARAMETER

UNIT CONDITIONS

min. typ. max. min. typ. max.

V V V T T t

r,tf

CC I O amb amb

DC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V DC input voltage range 0 V DC output voltage range 0 V

CC CC

V operating ambient temperature range −40 +85 −40 +85 °C see DC and AC operating ambient temperature range −40 +125 −40 +125 °C input rise and fall times except for

Schmitt-trigger inputs

1000

6.0

500 V

6.0 500 ns

400 V

CHAR. per device VCC= 2.0 V

= 4.5 V

= 6.0 V

Note

1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating supply voltage is 10 V.

March 1988 2

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS FOR 74HCU

SYMBOL PARAMETER

74HCU

min. typ. max.

amb

DC supply voltage 2.0 5.0 6.0 V DC input voltage range 0 V DC output voltage range 0 V operating ambient temperature range −40 +85 °C see DC and AC operating ambient temperature range −40 +125 °C

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

±I

DC supply voltage −0.5 +7V DC input diode current 20 mA for VI<−0.5 or VI> VCC+ 0.5 V DC output diode current 20 mA for VO<−0.5 or VO> VCC+ 0.5 V DC output source or sink

for −0.5 V < VO< VCC+ 0.5 V

current

standard outputs 25 mA bus driver outputs 35 mA

±I

;

±I

GND

DC VCCor GND current for types with:

standard outputs 50 mA bus driver outputs 70 mA

stg

tot

storage temperature range −65 +150 °C power dissipation per package for temperature range: −40 to +125 °C

74HC/HCT/HCU plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K

UNIT CONDITIONS

CHAR. per device

Note

1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating supply voltage is 11 V.

March 1988 3

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HC

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

HIGH level input voltage

LOW level input voltage

HIGH level output voltage

all outputs

HIGH level output voltage

standard outputs

HIGH level output voltage bus driver outputs

LOW level output voltage

all outputs

LOW level output voltage

standard outputs

LOW level output voltage

bus driver outputs

±I

input leakage current 0.1 1.0 1.0 µA 6.0 V

3-state OFF-state current

quiescent supply current

SSI 2.0 20.0 40.0 µA 6.0 V flip-flops 4.0 40.0 80.0 6.0 I MSI 8.0 80.0 160.0 6.0 I LSI 50.0 500 1000 6.0 I

amb

(°C)

TEST CONDITIONS

74HC

UNIT

(V)

min. typ. max. min. max. min. max.

1.5 1.2 1.5 1.5 V 2.0

3.15 2.4 3.15 3.15 4.5

4.2 3.2 4.2 4.2 6.0

0.8 0.5 0.5 0.5 V 2.0

2.1 1.35 1.35 1.35 4.5

2.8 1.8 1.8 1.8 6.0

1.9 2.0 1.9 1.9 V 2.0 V

4.4 4.5 4.4 4.4 4.5 −I

5.9 6.0 5.9 5.9 6.0 −I

3.98 4.32 3.84 3.7 V 4.5 V

5.48 5.81 5.34 5.2 6.0 −I

3.98 4.32 3.84 3.7 V 4.5 V

5.48 5.81 5.34 5.2 6.0 −I

0 0.1 0.1 0.1 V 2.0 V 0 0.1 0.1 0.1 4.5 I 0 0.1 0.1 0.1 6.0 I

0.15 0.26 0.33 0.4 V 4.5 V

0.16 0.26 0.33 0.4 6.0 I

0.15 0.26 0.33 0.4 V 4.5 V

0.16 0.26 0.33 0.4 6.0 I

or V

IL IH

IL CC

or GND

0.5 5.0 10.0 µA 6.0 V

or V

or GND

OTHER+25 −40 to +85 −40 to +125

−IO= 20 µA

= 20 µA

−IO= 4.0 mA = 5.2 mA

−IO= 6.0 mA = 7.8 mA

IO= 20 µA

= 20 µA

IO= 4.0 mA

= 5.2 mA

IO= 6.0 mA

= 7.8 mA

VO=V

or GND

IO= 0

= 0

March 1988 4

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HCT

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

HIGH level input voltage

LOW level input voltage

HIGH level output voltage

all outputs

HIGH level output voltage

standard outputs

HIGH level output voltage

bus driver outputs

LOW level output voltage

all outputs

LOW level output voltage

standard outputs

LOW level output voltage

bus driver outputs

±I

input leakage current

±I

3-state OFF-state current

quiescent supply current

SSI 2.0 20.0 40.0 µA 5.5 V flip-flops 4.0 40.0 80.0 5.5 I MSI 8.0 80.0 LSI 50.0 500 1000 5.5 I

amb

(°C)

TEST CONDITIONS

74HCT

UNIT

(V)

min. typ. max. min. max. min. max.

2.0 1.6 2.0 2.0 V 4.5 to

5.5

1.2 0.8 0.8 0.8 V 4.5 to

5.5

4.4 4.5 4.4 4.4 V 4.5 V

3.98 4.32

3.84 3.7 V 4.5 V

0 0.1 0.1 0.1 V 4.5 V

0.15 0.26

0.16 0.26

0.33 0.4 V 4.5 V

0.1 1.0 1.0 µA 5.5 V

0.5 5.0 10.0 µA 5.5 V

160.0 5.5 I

or V

IL IH

or V

IL IH

or V

IL IH

or V

IL IH

or V

IL IH

or V

or GND

or V

or GND

−IO= 20 µA

−IO= 4.0 mA

−IO= 6.0 mA

IO= 20 µA

IO= 4.0 mA

IO= 6.0 mA

VO=VCCor GND per input pin; other inputs at V

IO= 0

O O O

OTHER+25 −40 to +85 −40 to +125

or GND;

= 0

= 0 = 0 = 0

March 1988 5

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

(°C)

amb

74HCT

SYMBOL PARAMETER

UNIT

min. typ. max. min. max. min. max.

∆I

additional quiescent supply current per input pin for unit load coefﬁcient is 1 (note 1)

100 360 450 490 µA 4.5

Note

1. The additional quiescent supply current per input is determined by the ∆ICCunit load, which has to be multiplied by the unit load coefficient as given in the individual data sheets. For dual supply systems the theoretical worst-case (VI= 2.4 V; VCC= 5.5 V) specification is: ∆ICC= 0.65 mA (typical) and 1.8 mA (maximum) across temperature.

TEST CONDITIONS

(V)

−2.1 V

5.5

OTHER+25 −40 to +85 −40 to +125

other inputs at VCCor GND; I

March 1988 6

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

DC CHARACTERISTICS FOR 74HCU

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

HIGH level input voltage

LOW level input voltage

HIGH level output voltage

LOW level output voltage

±I

input leakage current 0.1 1.0 1.0 µA 6.0 V

quiescent supply current SSI

amb

(°C)

TEST CONDITIONS

74HCU

UNIT

(V)

min. typ. max. min. max. min. max.

1.7 1.4 1.7 1.7 V 2.0

3.6 2.6 3.6 3.6 4.5

4.8 3.4 4.8 4.8 6.0

0.6 0.3 0.3 0.3 V 2.0

1.9 0.9 0.9 0.9 4.5

2.6 1.2 1.2 1.2 6.0

1.8 2.0 1.8 1.8 V 2.0 V

4.0 4.5 4.0 4.0 4.5 −I

5.5 6.0 5.5 5.5 6.0 −I

3.98 4.32 3.84 3.7 V 4.5 V

5.48 5.81 5.34 5.2 6.0 −I

or V

GND 0 0.2 0.2 0.2 V 2.0 V 0 0.5 0.5 0.5 4.5 I 0 0.5 0.5 0.5 6.0 I

0.15 0.26 0.33 0.4 V 4.5 V

0.16 0.26 0.33 0.4 6.0 I

GND

2.0 20.0 40.0 µA 6.0 V

GND

OTHER+25 −40 to +85 −40 to +125

−IO= 20 µA

= 20 µA

−IO= 4.0 mA = 5.2 mA

IO= 20 µA

= 20 µA

IO= 4.0 mA

= 5.2 mA

IO=0

March 1988 7

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

THL

/ t

output transition time

TLH

standard outputs

THL

/ t

output transition time

TLH

bus driver outputs

AC CHARACTERISTICS FOR 74HCU

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

THL

/ t

output transition time 19 75 95 110 ns 2.0 Fig.1

TLH

amb

(°C)

TEST CONDITIONS

74HC

+25 −40 to +85 −40 to +125

UNIT

(V)

min. typ. max. min. max. min. max.

19 75 95 110 ns 2.0 Figs 3 and 4 7 15 19 22 4.5 6 13 16 19 6.0 14 60 75 90 ns 2.0 Figs 3 and 4 5 12 15 18 4.5 4 10 13 15 6.0

amb

(°C)

TEST CONDITIONS

74HCU

+25 −40 to +85 −40 to +125

UNIT

(V)

min. typ. max. min. max. min. max.

7 15 19 22 4.5 6 13 16 19 6.0

WAVEFORMS

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

THL

/ t

output transition time

TLH

standard outputs

output transition time

TLH

bus driver outputs

7 15 19 22 ns 4.5 Figs 8 and 9

5 12 15 18 ns 4.5 Figs 8 and 9

March 1988 8

(°C)

amb

74HCT

UNIT

TEST CONDITIONS

WAVEFORMS

(V)

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

HCU TYPES AC waveforms 74HCU

Fig.1 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

Test circuit for 74HCU

handbook, halfpage

INPUT

OUTPUT

handbook, halfpage

PULSE

GENERATOR

PHL

10%

THL

90%

50%

10%

PLH

TLH

CL50 pF

GND

MGK564

MGK565

D.U.T

CL= load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

= termination resistance should be equal to the output impedance Zoof

the pulse generator.

Fig.2 Test circuit.

March 1988 9

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

HC TYPES AC waveforms 74HC

handbook, halfpage

INPUT

OUTPUT

PHL

10%

THL

90%

50%

10%

PLH

TLH

GND

MGK564

Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

AC waveforms 74HC

handbook, full pagewidth

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET,

RESET,

PRESET

INPUT

(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET

and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals are specified in the individual device data sheet.

(2) For AC measurements: t

= 6 ns; when measuring f

r=tf

10 %

50%

rem

50%

90%

50%

10%

PLH

1/f

max t

90%

50%

, there is no constraint on tr,tfwith 50% duty factor.

max

TLH

PHL

THL

GND

MGK569

Fig.4 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for

sequential logic ICs.

March 1988 10

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

Test circuit for 74HC

handbook, halfpage

PULSE

GENERATOR

CL= load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

= termination resistance should be equal to the output impedance Zoof

the pulse generator.

AC waveforms 74HC (continued)

handbook, full pagewidth

OUTPUT ENABLE

OUTPUT LOW-to-OFF OFF-to-LOW

OUTPUT HIGH-to-OFF OFF-to-HIGH

90%

50%

Fig.5 Test circuit.

10%

PLZ

PHZ

10%

90%

D.U.T

CL50 pF

PZL

PZH

MGK565

50%

GND

MGK562

outputs

enabled

Fig.6 Propagation delays of 3-state outputs.

March 1988 11

outputs

disabled

outputs enabled

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

Test circuit for 74HC

handbook, full pagewidth

PULSE

GENERATOR

Switch position

TEST SWITCH t

PZH

PZL

PHZ

PLZ

GND V

Note

1. For open-drain N-channel outputs t

CL= load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

= termination resistance should be equal to the output impedance Zoof

the pulse generator.

PLZ

and t

D.U.T

are applicable.

PZL

CL50 pF

RL = 1 kΩ

MGK563

Fig.7 Test circuit for 3-state outputs.

HCT TYPES AC waveforms 74HCT

PHL

10%

THL

90%

1.3 V

1.3 V 10%

handbook, halfpage

INPUT

OUTPUT

Fig.8 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

March 1988 12

3 V

PLH

TLH

GND

MGK567

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

AC waveforms 74HCT

handbook, full pagewidth

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET,

RESET,

PRESET

INPUT

(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals

(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals are specified in the individual device data sheet.

(2) For AC measurements: t

= 6 ns; when measuring f

r=tf

10%

1.3 V

rem

1.3 V

10%

90%

1.3 V

PLH

1/f

max t

90%

1.3 V

, there is no constraint on tr,tfwith 50% duty factor.

max

TLH

PHL

THL

3 V

GND

3 V

GND

3 V

GND

MGK568

Fig.9 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for

sequential logic ICs.

Test circuit for 74HCT

handbook, halfpage

PULSE

GENERATOR

CL= load capacitance including jig and probe capacitance (see AC

CHARACTERISTICS for values).

= termination resistance should be equal to the output impedance Zoof

the pulse generator.

D.U.T

CL50 pF

MGK565

Fig.10 Test circuit.

March 1988 13

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

AC waveforms 74HCT (continued)

handbook, full pagewidth

Test circuit for 74HCT

handbook, full pagewidth

OUTPUT

ENABLE

OUTPUT LOW-to-OFF OFF-to-LOW

OUTPUT HIGH-to-OFF OFF-to-HIGH

MGK566

PULSE

GENERATOR

90%

1.3 V 10%

PLZ

outputs

enabled

10%

PHZ

90%

outputs

disabled

PZL

1.3 V

PZH

1.3 V

Fig.11 Propagation delays of 3-state outputs.

D.U.T

CL50 pF

RL = 1 kΩ

outputs enabled

Switch position

TEST SWITCH t

PZH

PZL

PHZ

PLZ

GND V

Note

1. For open-drain N-channel outputs t

CL= load capacitance including jig and probe capacitance

(see AC CHARACTERISTICS for values).

= termination resistance should be equal to the output impedance Zoof

the pulse generator.

PLZ

and t

are applicable.

PZL

Fig.12 Test circuit for 3-state outputs.

March 1988 14

MGK563

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

DATA SHEET SPECIFICATION GUIDE

INTRODUCTION

The 74HCMOS data sheets have been designed for ease-of-use. A minimum of cross-referencing for more information is needed.

TYPICAL PROPAGATION DELAY AND FREQUENCY

The typical propagation delays listed at the top of the data sheets are the average of t

PLH

and t

for the longest data

PHL

path through the device with a 15 pF load. For clocked devices, the maximum frequency of operation

is also given. The typical operating frequency is the maximum device operating frequency with a 50% duty factor and no constraints on tr and tf.

LOGIC SYMBOLS

Two logic symbols are given for each device - the conventional one (Logic Symbol) which explicitly shows the internal logic (except for complex logic) and the IEC Logic Symbol as developed by the IEC (International Electrotechnical Commission).

The IEC has been developing a very powerful symbolic language that can show the relationship of each input of a digital logic current to each output without explicitly showing the internal logic. Internationally, Working Group 2 of IEC Technical Committee TC-3 has prepared a new document (Publication 617-12) which supersedes Publication 117-15, published in 1972.

RATINGS

The “RATINGS” table (Limiting values in accordance with the Absolute Maximum System - IEC134) lists the maximum limits to which the device can be subjected without damage. This doesn’t imply that the device will function at these extreme conditions, only that, when these conditions are removed and the device operated within the Recommended Operating Conditions, it will still be functional and its useful life won’t have been shortened.

The maximum rated supply voltage of 7 V is well below the typical breakdown voltage of 18 V.

RECOMMENDED OPERATING CONDITIONS

The “RECOMMENDED OPERATING CONDITIONS” table lists the operating ambient temperature and the

conditions under which the limits in the “DC CHARACTERISTICS” and “AC CHARACTERISTICS” tables will be met. The table should not be seen as a set of limits guaranteed by the manufacturer, but as the conditions used to test the devices and guarantee that they will then meet the limits in the DC and AC CHARACTERISTICS tables.

DC CHARACTERISTICS

The “DC CHARACTERISTICS” table reflects the DC limits used during testing. The values published are guaranteed.

The threshold values of V

and VIL can be tested by the

user. If VIH and VIL are applied to the inputs, the output voltages will be those published in the “DC CHARACTERISTICS” table. There is a tendency, by some, to use the published VIH and VIL thresholds to test a device for functionality in a “function-table exercizer” mode. This frequently causes problems because of the noise present at the test head of automated test equipment with cables up to 1 metre. Parametric tests, such as those used for the output levels under the VIH and VIL conditions are done fairly slowly, in the order of milliseconds, so that there is no noise at the inputs when the outputs are measured. But in functionality testing, the outputs are measured much faster, so there can be noise on the inputs, before the device has assumed its final and correct output state. Thus, never use VIH and VIL to test the functionality of any HCMOS device type; instead, use input voltages of VCC (for the HIGH state) and 0 V (for the LOW state). In no way does this imply that the devices are noise-sensitive in the final system.

In the data sheets, it may appear strange that the typical VIL is higher than the maximum VIL. However, this is because V

is the maximum VIL (guaranteed) for all

ILmax

devices that will be recognized as a logic LOW. However, typically a higher VIL will also be recognized as a logic LOW. Conversely, the typical VIH is lower than its minimum guaranteed level.

For 74HCMOS, unlike TTL, no output HIGH short-circuit current is specified. The use of this current, for example, to calculate propagation delays with capacitive loads, is covered by the HCMOS graphs showing the output drive capability and those showing the dependence of propagation delay on load capacitance.

The quiescent supply current ICC is the leakage current of all the reversed-biased diodes and the OFF-state MOS transistors. It is measured with the inputs at VCC or GND and is typically a few nA.

March 1988 15

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

AC CHARACTERISTICS

The “AC CHARACTERISTICS” table lists the guaranteed limits when a device is tested under the conditions given in the AC Test Circuits and Waveforms section.

TEST CIRCUITS

Good high-frequency wiring practices should be used in test circuits. Capacitor leads should be as short as possible to minimize ripples on the output waveform transitions and undershoot. Generous ground metal (preferably a ground-plane) should be used for the same reasons. A V at the test socket, also with short leads. Input signals should have rise and fall times of 6 ns, a signal swing of 0 V to VCC for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz square wave is recommended for most propagation delay tests. The repetition rate must be increased for testing f

. Two pulse generators are usually required for testing

max

such parameters as set-up time, hold time and removal time. f

max

with a 50% duty factor, but for typical f 60 MHz, there are no constraints on rise and fall times.

decoupling capacitor should be provided

is also tested with 6 ns input rise and fall times,

as high as

max

March 1988 16

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

DEFINITIONS OF SYMBOLS AND TERMS USED IN HCMOS DATA SHEETS

Currents

Positive current is deﬁned as conventional current ﬂow into a device. Negative current is deﬁned as conventional current ﬂow out of a device.

Quiescent power supply current; the current ﬂowing into the VCC supply terminal.

∆I

Additional quiescent supply current per input

pin at a speciﬁed input voltage and VCC.

GND

Quiescent power supply current; the current ﬂowing into the GND terminal.

Input leakage current; the current ﬂowing into a device at a speciﬁed input voltage and VCC.

Input diode current; the current ﬂowing into a device at a speciﬁed input voltage.

Output source or sink current: the current ﬂowing into a device at a speciﬁed output voltage.

Output diode current; the current ﬂowing into a device at a speciﬁed output voltage.

OFF-state output current; the leakage current ﬂowing into the output of a 3-state device in the OFF-state, when the output is connected to VCC or GND.

Analog switch leakage current; the current ﬂowing into an analog switch at a speciﬁed voltage across the switch and VCC.

V V

Analog terms

∆R

Capacitances

LOW level input voltage; the range of input

voltages that represents a logic LOW level in the system.

HIGH level output voltage; the range of

voltages at an output terminal with a speciﬁed output loading and supply voltage. Device inputs are conditioned to establish a HIGH level at the output.

LOW level output voltage; the range of voltages

at an output terminal with a speciﬁed output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output.

Trigger threshold voltage; positive-going signal.

T+

− Trigger threshold voltage; negative-going

signal.

ON-resistance; the effective ON-state

resistance of an analog switch, at a speciﬁed voltage across the switch and output load.

∆ON-resistance; the difference in

ON-resistance between any two switches of an analog device at a speciﬁed voltage across the switch and output load.

Voltages

All voltages are referenced to GND (ground), which is typically 0 V.

GND Supply voltage; for a device with a single

negative power supply, the most negative power supply, used as the reference level for other voltages; typically ground.

Supply voltage; the most positive potential on

the device.

Supply voltage; one of two (GND and VEE)

negative power supplies.

Hysteresis voltage; difference between the

trigger levels, when applying a positive and a negative-going input signal.

HIGH level input voltage; the range of input

voltages that represents a logic HIGH level in the system.

March 1988 17

Input capacitance; the capacitance measured

at a terminal connected to an input of a device.

Input/Output capacitance; the capacitance

I/O

measured at a terminal connected to an I/O-pin (e.g. a transceiver).

Output load capacitance; the capacitance

connected to an output terminal including jig and probe capacitance.

Power dissipation capacitance; the capacitance

used to determine the dynamic power dissipation per logic function, when no extra load is provided to the device.

Switch capacitance; the capacitance of a

terminal to a switch of an analog device.

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

AC switching parameters

max

PHL

PLH

PHZ

Input frequency; for combinatorial logic devices

PLZ

the maximum number of inputs and outputs switching in accordance with the device function table. For sequential logic devices the clock frequency using alternate HIGH and LOW for data input or using the toggle mode, whichever is applicable.

Output frequency; each output. Maximum clock frequency; clock input

waveforms should have a 50% duty factor and

PZH

be such as to cause the outputs to be switching from 10%VCC to 90%VCC in accordance with the device function table.

Hold time; the interval immediately following the active transition of the timing pulse (usually the clock pulse) or following the transition of the control input to its latching level, during which interval the data to be recognized must be

maintained at the input to ensure their

PZL

continued recognition. A negative hold time indicates that the correct logic level may be released prior to the timing pulse and still be recognized.

Clock input rise and fall times; 10% and 90% values.

Propagation delay; the time between the speciﬁed reference points, normally the 50% points for 74HC and 74HCU devices on the

rem

input and output waveforms and the 1.3 V points for the 74HCT devices, with the output changing from the deﬁned HIGH level to the deﬁned LOW level.

Propagation delay; the time between the speciﬁed reference points, normally the 50% points for 74HC and 74HCU devices on the input and output waveforms and the 1.3 V point

for the 74HCT devices, with the output changing from the deﬁned LOW level to the deﬁned HIGH level.

3-state output disable time; the time between the speciﬁed reference points, normally the 50% points for the 74HC and 74HCU devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and a

3-state output disable time; the time between the speciﬁed reference points, normally the 50% points for the 74HC devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and a point representing 10% of the output swing on the output voltage waveform of a 3-state device, with the output changing from a LOW level (VOL) to a high impedance OFF-state (Z).

3-state output enable time; the time between the speciﬁed reference points, normally the 50% points for the 74HC devices and 1.3 V points for the 74HCT devices on the output enable input voltage waveform and the 50% point on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state (Z) to a HIGH level (VOH).

3-state output enable time; the time between the speciﬁed reference points, normally the 50% points for the 74HC devices and the 1.3 V points for the 74HCT devices on the output enable input voltage waveform and the 50% point on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state (Z) to a LOW level (VOL).

Removal time; the time between the end of an overriding asynchronous input, typically a clear or reset input, and the earliest permissible beginning of a synchronous control input, typically a clock input, normally measured at the 50% points for 74HC devices and the 1.3 V points for the 74HCT devices on both input voltage waveforms.

Set-up time; the interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their recognition. A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.

point representing 10% of the output swing on the output voltage waveform of a 3-state device, with the output changing from a HIGH level (VOH) to a high impedance OFF-state (Z).

March 1988 18

Philips Semiconductors

HCMOS family characteristics FAMILY SPECIFICATIONS

THL

Output transition time; the time between two speciﬁed reference points on a waveform, normally 90% and 10% points, that is changing from HIGH-to-LOW.

Output transition time; the time between two speciﬁed reference points on a waveform, normally 10% and 90% points, that is changing from LOW-to-HIGH.

Pulse width; the time between the 50% amplitude points on the leading and trailing edges of a pulse for 74HC and 74HCU devices and at the 1.3 V points for 74HCT devices.

March 1988 19

Philips HCMOS Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual