Philips GTL2010 Datasheet
INTEGRATED CIRCUITS
GTL2010
10-bit GTL Processor Voltage Clamp
Product specification 1999 Apr 05
Philips Semiconductors Product specification
GTL201010-bit GTL Processor Voltage Clamp
FEA TURES
•Direct interface with TTL level
•6.5Ω ON-state connection between port S
DESCRIPTION
The GTL2010 is a high speed 10-bit voltage clamp. The low
ON-state resistance of the clamp allows connections to be made
with minimal propagation delay.
The device is organized as one 10-bit voltage clamp. When S or D
is low, the clamp is in the ON–state and a low resistance connection
exists between the S and D ports. When S port and D port are high,
the clamp is in the OFF-state and a very high impedance exists
between the S and D ports. When port D is high, the voltage on the
S port is clamped to the applied reference voltage on the GREF
port.
QUICK REFERENCE DA TA
SYMBOL PARAMETER
Propagation delay
Sn to Dn
Channel capacitance (OFF-state) VS = 1.5V 7.5 pF
C
t
PLH
OFF
and D
n
n
V
= 3.3V; V
DD1
V
= 1.5V; unloaded
REF
PIN CONFIGURATION
GND
S
REF
S
CONDITIONS
T
= 25°C; GND = 0V
amb
= 2.5V;
DD2
1
2
S
3
1
S
4
2
5
S
3
6
S
4
7
S
5
S
8
6
S
9
7
S
10
8
S
11
9
12
10
G
24
D
23
22
21
20
19
18
17
16
15
14
13
D
SA00527
D
D
D
D
D
D
D
D
D
REF
REF
1
2
3
4
5
6
7
8
9
10
TYPICAL UNIT
1.5 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
24-Pin Plastic TSSOP Type II 0°C to +85°C GTL2010 PW GTL2010PW DH SOT355–1
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 GND Ground (0V)
2 S
3 – 12 S
13 – 22 D
23 D
24 G
REF
n
n
REF
REF
Source of reference
transistor
Port S1 to Port S
Port D1 to Port D
Drain of reference
transistor
Gate of reference
transistor
FUNCTION TABLE
S
N
L L
H H
H = High voltage level
L = Low voltage level
Z = High impedance “off” state
D
N
10
10
CLAMP SCHEMATIC
D
REF
S
REF
G
REF
D
1
S
1
D
10
S
10
SA00526
1999 Apr 05 853-2153 21178
2
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