Philips GTL2004 Datasheet

INTEGRATED CIRCUITS

GTL2004

Quad GTL/GTL+ to LVTTL/TTL
bidirectional latched translator

Product specification
Supersedes data of 1999 May 15

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1999 Jul 19

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

Quad GTL/GTL+ to LVTTL/TTL
bidirectional latched translator

FEA TURES

•Operates as a quad GTL/GTL

LVTTL/TTL to GTL/GTL+ driver

•Quad bidirectional bus interface

•Separate latch enable for each bit

•Live insertion/extraction permitted

•B outputs include 30Ω series resistance

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per JEDEC Std

DESCRIPTION

The GTL2004 is a quad translating transceiver designed for 3.3V
system interface with a GTL/GTL

The direction pin allows the part to function as either a GTL to TTL
sampling receiver or as a TTL to GTL interface. Separate latch
enables allow sampling and holding of data from the GTL bus.

+

sampling receiver or as a

+

bus.

GTL2004

PIN CONFIGURATION

1A0
2

LE0

A1

3
4

LE1

A2

5

LE2

6

A3

7

GND

8

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

15 DIR Direction control input

1, 3, 5, 7 A0 – A3 Data inputs/outputs (A side, GTL)

11, 12, 13, 14 B0 – B3 Data inputs/outputs (B side, TTL)

2, 4, 6, 9 LE0 – LE3 Latch enables

10 GTLREF GTL reference voltage

8 GND Ground (0V)

16 V

CC

V

16

CC

DIR

15
14

B0

B1

13

B2

12
11

B3
GTLREF

10

9

LE3

SW00318

Positive supply voltage

QUICK REFERENCE DATA

TYPICAL

B to A A to B

2.0

1.8

4.4

4.7

3.0 3.0 pF

t

PLH

t

PHL

C

C

I/O

CONDITIONS

T

= 25°C

amb

Propagation delay
An to Bn or Bn to An

IN

Input capacitance DIR, LEn VI = 0V or V
I/O pin capacitance Outputs disabled; V

CL = 50pF; VCC = 3.3V

CC

I/O

= 0V or 3.152V 7.2 4.6 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

16-Pin Plastic TSSOP Type II –40°C to +85°C GTL2004 PW DH SOT403-1

ns

1999 Jul 19 853–2165 21984

2

Philips Semiconductors Product specification

Quad GTL/GTL+ to LVTTL/TTL
bidirectional latched translator

LOGIC SYMBOL

A0

LE0

A1

LE1

A2

LE2

LATCH

LATCH

LATCH

GTL2004

FUNCTION TABLE

INPUT INPUT/OUTPUT

DIR LEn A B

L H Inputs An = Bn
L L X NC

B0

B1

B2

H X Bn = An Inputs

H = HIGH voltage level
L = LOW voltage level
X = Don’t care
NC = No change

A3

LE3

GTLREF DIR

LATCH

B3

SW00319

1999 Jul 19

3