Philips GTL2000DB Datasheet
GTL2000
22-bit GTL Processor Voltage Clamp
Product specification 1999 Apr 05
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
GTL200022-bit GTL Processor Voltage Clamp
2
1999 Apr 05 853-2154 21178
FEA TURES
•Direct interface with TTL level
•6.5Ω ON-state connection between port S
n
and D
n
DESCRIPTION
The GTL2000 provides twenty-two bits of high-speed voltage
clamps. The low ON-state resistance of the clamp allows
connections to be made with minimal propagation delay.
The device is organized as one 22-bit voltage clamp. When S or D
is low the clamp is in the ON–state and a low resistance connection
exists between the S and D ports. When S port and D port are high,
the clamp is in the OFF-state and a very high impedance exists
between the S and D ports. When the D port is high, the voltage on
the S port is clamped to the applied reference voltage on the GREF
port.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
S
REF
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
S
17
S
18
S
19
S
20
S
21
S
22
G
REF
D
REF
GND
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
D
16
D
17
D
18
D
19
D
20
D
21
D
22
SA00521
QUICK REFERENCE DA TA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
Propagation delay
Sn to Dn
V
DD1
= 3.3V; V
DD2
= 2.5V;
V
REF
= 1.5V; unloaded
1.5 ns
C
OFF
Channel capacitance (OFF-state) VS = 1.5V 7.5 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type II 0°C to +85°C GTL2000 DB GTL2000 DB SOT370–1
Philips Semiconductors Product specification
GTL2000
22-bit GTL Processor Voltage Clamp
1999 Apr 05
3
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 GND Ground (0V)
2 S
REF
Source of reference
transistor
3 – 24 S
n
Port S1 to Port S
22
25 – 46 D
n
Port D1 to Port D
22
47 D
REF
Drain of reference
transistor
48 G
REF
Gate of reference
transistor
FUNCTION TABLE
S
N
D
N
L L
H H
H = High voltage level
L = Low voltage level
Z = High impedance “off” state
CLAMP SCHEMA TIC
SA00522
S
REF
S
1
S
22
D
REF
D
1
D
22
G
REF
ABSOLUTE MAXIMUM RA TINGS
1, 2, 3
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
S_REF
DC source reference voltage –0.5 to +7.0 V
V
D_REF
DC drain reference voltage –0.5 to +7.0 V
V
G_REF
DC gate reference voltage –0.5 to +7.0 V
V
Sn
DC voltage Port S
n
–0.5 to +7.0 V
V
Dn
DC voltage Port D
n
–0.5 to +7.0 V
I
REFK
DC reference diode current VI < 0 –50 mA
I
SK
DC diode current Port S
n
VI < 0 –50 mA
I
DK
DC diode current Port D
n
VI < 0 –50 mA
I
MAX
DC clamp current per channel Channel in ON-state ±35 mA
T
stg
Storage temperature range –65 to +150 °C
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
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