Philips f199 DATASHEETS

Philips Semiconductors FAST Products Product specification

74F1998-bit parallel-access shift register

1

June 15, 1988 853–0082 93568

FEATURES

•Buffered clock and control inputs

•Shift right and parallel load capability

•Fully synchronous data transfers

•J-K(D) inputs to first stage

•Clock enable for hold (do nothing) mode

•Asynchronous Master Reset

DESCRIPTION

The 74F199 is an 8-bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. The device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial-to-parallel,
or parallel–to-serial data transfers at very high speeds.

The 74F199 operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE

) input. Serial data enters the first flip-flop (Q0) via the J

and K

inputs when the PE input is High, and is shifted one bit in the

direction Q0→Q1→Q2 following each Low-to-High clock transition.
The J and K

inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.

The device appears as eight common clocked D flip-flops when the
PE

input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D7) is transferred to the respective Q0–Q7
outputs.

All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F199 utilizes
edge-triggered, therefore there is no restriction on the activity of the
J, K

, Dn, and PE inputs for logic operation, other than the setup and

hold time requirements.
A Low on the Master Reset (MR

) input overrides all other inputs and
clears the register asynchronously forcing all bit positions to a Low
state.

PIN CONFIGURATION

SF00152

1
2
3
4
5
6
7
8

9
10
11
12 13

14

15

16

17

18

19

20

21

22

23

24

K

J
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CE

V

CC

PE
D7
Q7
D6
Q6
D5

D4

Q5

Q4
MR
CP

GND

TYPE TYPICAL f

MAX

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F199 95MHz 70mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V ±10%, T

amb

= 0°C to +70°C

24-pin plastic slim DIP

(300mil)

N74F199N

24-pin plastic SOL N74F199D

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

D0–D7 Parallel data inputs 1.0/1.0 20µA/0.6mA

J, K J and K inputs 1.0/1.0 20µA/0.6mA

PE Parallel Enable input 1.0/1.0 20µA/0.6mA
CE Clock Enable input 1.0/1.0 20µA/0.6mA
DP Clock Pulse inputs (Active rising edge) 1.0/1.0 20µA/0.6mA

MR Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA

Q0–Q7 Data outputs 50/33 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

Philips Semiconductors FAST Products Product specification

74F1998-bit parallel-access shift register

June 15, 1988

2

LOGIC SYMBOL

Q0 Q1 Q2 Q3

4 6 8 10

V

CC

= Pin 24

GND = Pin 12

23

2

1

13

11

14

PE
J
K
CP
CE
MR

D1 D2

7 9

SF00153

D3D0

3 5

Q5 Q6 Q7

15 17 19 21

D5 D6

20 22

D7D4

16 18

Q4

IEEE/IEC SYMBOL

SF00154

1

9
16
18
20
22

1

3

5

7

2

14

23

13

11

1

&

C2/→

SRG8

C3
R

2J
2K
2, 3D
2, 3D

10
15
17
19
21

4

6
8

FUNCTION TABLE

INPUTS OUTPUTS

MR CP CE PE J K Dn Q0 Q1 … Q6 Q7

OPERATING MODES

L X X X X X X L L … L L Reset (clear
H ↑ l h h h X H q0 … q5 q6 Shift, set First stage
H ↑ l h l l X L q0 … q5 q6 Shift, reset First stage
H ↑ l h h l X q0 q0 … q5 q6 Shift, toggle First stage
H ↑ l h l h X q0 q0 … q5 q6 Shift, retain First stage
H ↑ l l X X dn d0 d1 … d6 d7 Parallel load
H ↑ h X X X X q0 q1 … q6 q7 Hold (do nothing)

H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior t the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition

Philips Semiconductors FAST Products Product specification

74F1998-bit parallel-access shift register

June 15, 1988

3

LOGIC DIAGRAM

CP
RD

R S

Q

22

D7

21

Q7

CP
RD

R S

Q

20

D6

19

Q6

CP
RD

R S

Q

18

D5

17

Q5

CP
RD

R S

Q

16

D4

15

Q4

CP
RD

R S

Q

9

D3

10

Q3

CP
RD

R S

Q

7

D2

8

Q2

CP
RD

R S

Q

5

D1

6

Q1

CP
RD

R S

Q

4

Q0

Q

3

D0

14

MR

1

K

2

J

23

PE

13

CP

11

CE

SF00155