Philips f160s5tl70a Service Manual

PRODUCT SPECIFICATIONS

Integrated Circuits Group

LH28F160S5T-L70A

Flash Memory

16M (2M × 8/1M × 16)

(Model No.: LHF16K55)

Spec No.: EL104104

Issue Date: April 17, 1998

SHARP

LHF16K55

l Handle this document carefully for it contains material protected by international copyright

law. Any reproduction, full or in part, of this material is prohibited without the express

written permission of the company.

l When using the products covered herein, please observe the conditions written herein

and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following

application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application -areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3).

*Office electronics

alnstrumentation and measuring equipment *Machine tools *Audiovisual equipment

*Home appliance &ommunication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment

which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring &liability and safety of the equipment and the overall system.

*Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment

*Mainframe computers

l Traff ic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands

extremely high performance in terms of functionality, reliability, or accuracy.

*Aerospace equipment @Communications equipment for trunk lines

*Control equipment for the nuclear power industry *Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above

three Paragraphs to a sales representative of the company.

l Please direct all queries regarding the products covered herein to a sales representative

of the company.

‘.

Rev.1.8

SHARI=

LHFl6K55

CONTENTS

PAGE PAGE

1 INTRODUCTION ......................................................

1 .l Product Overview.. .............................................. 3

2 PRINCIPLES OF OPERATION.. ..............................

2.1 Data Protection ...................................................

3 BUS OPERATION ....................................................

3.1 Read ................................................................... 7

3.2 Output Disable ....................................................

3.3 Standby ............................................................... 7

3.4 Deep Power-Down .............................................. 7

3.5 Read identifier Codes Operation..

3.6 Query Operation.. ................................................

3.7 Write ....................................................................

3 COMMAND DEFINITIONS ....................................... 8

4.1 Read Array Command.. .....................................

4.2 Read Identifier Codes Command.. .................... 11

4.3 Read Status Register Command.. ..................... 11

4.4 Clear Status Register Command.. ..................... 11

4.5 Query Command.. ............................................. 12

4.51 Block Status Register .................................. 12

4.5.2 CFI Query Identification String.. ................... 13

4.5.3 System interface Information ....................... 13

4.5.4 Device Geometry Deffnition ......................... 14

4.5.5 SCS OEM Specific Extended Query Table . . 14

4.6 Block Erase Command ......................................

4.7 Full Chip Erase Command.. .............................. 15

4.8 Word/Byte Write Command.. ............................. 16

4.9 Multi Word/Byte Write Command.. .................... 16

4.10 Block Erase Suspend Command.. ................... 17

4.11 (Multi) Word/Byte Write Suspend Command

4.12 Set Block Lock-Bit Command..

4.13 Clear Block Lock-Bits Command.. ...................

4.14 STS Configuration Command ......................... 19

....................... 8

1 1

... 17

........................ 18

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control ................................ .3C

5.2 STS and Block Erase, Full Chip Erase, (Multi)

6 7

8 8

Word/Byte Write and Block Lock-Bit Configuration

Polling.. ............................................................. .3C

5.3 Power Supply Decoupling.. ................................ 3C

5.4 V,, Trace on Printed Circuit Boards..

5.5 V,,, V,,, RP# Transitions..

5.6 Power-Up/Down Protection..

5.7 Power Dissipation

6 ELECTRICAL SPECIFICATIONS.. ........................ .3i

6.1 Absolute Maximum Ratings ............................... 32

6.2 Operating Conditions ......................................... 32

6.2.1 Capacitance .................................................

6.2.2 AC Input/Output Test Conditions..

6.2.3 DC Characteristics.. ..................................... .34

6.2.4 AC Characteristics - Read-&ly Operations .36

6.2.5 AC Characteristics - Write Operations..

6.2.6 Alternative CE#-Controlled

6.2.7 Reset Operations ......................................... 43

6.2.8 Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit

Configuration Performance.. ......................... 44

7 ADDITIONAL INFORMATION ....................... . ....... .45

7.1 Ordering Information

8 PACKAGE AND PACKING SPECIFICATION;;......4 6

............................................. .31

................................ .3C

............... .3C

..............................

.............................

...............

Writes.. ............. .41

................................ .I ........ 45

.......

.31 .31

.3C

.3S

Rev. 1.8

SHARI=

16-MBIT (2MBx8/1 MBxl6)

Smart 5 Flash MEMORY

Smart 5 Technology

- 5V vcc

- 5V vpp

Common Flash Interface (CFI)

Universal & Upgradable Interface

Scalable Command Set (SCS)

High Speed Write Performance

32 Bytes x 2 plane Page Buffer

2ys/Byte Write Transfer Rate

High Speed Read Performance

- 70ns(5V=0.25V), 80ns(5VT0.5V)

LHFl6K55

LH28F160S5T-L70A

Enhanced Data Protection Features

Absolute Protection with Vpp=GND

Flexible Block Locking

Erase/Write Lockout during Power

Transitions

Extended Cycling Capability

100,000 Block Erase Cycles

3.2 Million Block Erase Cycles/Chip

Low Power Management

Deep Power-Down Mode

Automatic Power Savings Mode

Decreases ICC in Static Mode

Enhanced Automated Suspend Options

Write Suspend to Read

Block Erase Suspend to Write

Block Erase Suspend to Read

High-Density Symmetrically-Blocked Architecture

Thirty-two 64-Kbyte Erasable Blocks

SRAM-Compatible Write Interface

User-Configurable x8 or x16 Operation

SHARP’s LH28F160S5T-L70A Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S5T-L70A offers three levels of protection: absolute protection with V,, at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

The LH28F160SST-L70A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs.

Automated Write and Erase

Command User Interface

- Status Register

Industry-Standard Packa;ing

- 56-Lead TSOP

ETOXTM’ V Nonvolatile Flash

Technology

Not designed or rated as radiation hardened

The LH28F160S5T-L70A is manufactured on SHARP’s 0.4pm ETOX standard package: the 56-Lead TSOP, ideal for

‘ETOX is a trademark of Intel Corporation.

board constrained applications.

TM* V process technology. It come in industry-

Rev. 1.8

SHARP

LHFI 6K55

1 INTRODUCTION

This specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications.

datasheet contains

LH28F160.%T-L70A

1 .l Product Overview

The LH28F160S5T-L70A is a high-performance 16-

Mbit Smart 5 Flash memory organized as

2MBx8/1MBxl6. The 2MB of data is arranged in thirty-two 64-Kbyte blocks which are individually

erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3.

Smart 5 technology provides a choice of Vcc and V,, combinations, as shown in Table 1, to meet system performance and power expectations. 5V Voc provides the highest read performance. V,, at 5V eliminates the need for a separate 12V converter, while V,,=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated V,, pin gives complete data protection when V,, < VppLK.

Table 1. V,, and VP, Voltage Combinations

Offered by Smart 5 Technology

Vcr: Voltage Vpp Voltage

5v 5v

Internal automatically configures the device for optimized read and write operations.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence

nritten to the CUI initiates device automation. An

nternal Write State Machine (WSM) automatically executes the algorithms and timings necessary for slack erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations.

4 block erase operation erases one of the device’s ?4-Kbyte blocks typically within 0.34s (5V Vcc, 5V Jpp) independent of other blocks. Each block can be ndependently erased 100,000 times (3.2 million Ilock erases per device). Block erase suspend mode 1110~s system software to suspend block erase to ,ead or write data from any other block.

4 word/byte write is performed in byte increments ypically within 9.241s (5V Vco, 5V VP,). A multi vord/byte write has high speed write performance of !us/byte (5V Voc, 5V V,,). (Multi) Word/byte write cuspend mode enables the system to read data or

vcc

and

detection Circuitry

execute code from any other flash memory array

location. Individual block locking uses a combination of bits

and WP#, Thirty-two block lock-bits, to lock and

unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. Block lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) se1 and cleared block lock-bits.

The status register indicates when the WSM’s block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished.

The STS output gives an additional indicator of WSM

activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for

example). Status polling using STS minimizes both CPU overhead and system power consumption. STS

pin can be configured to different states using the

Configuration command. The STS pin defaults to

RY/BY# operation. When low, STS indicates that the

WSM is performing a block erase, full chip erase,

(multi) word/byte write or block lock-bit configuration.

STS-High Z indicates that the WSM is ready for a

new command, block erase is suspended and (multi)

word/byte write are inactive, (m!&i) word/byte write are suspended, or the device is In deep power-down mode. The other 3 alternate configurations are all pulse mode for use as a system interrupt.

The access time is 70ns (t,vQv) over the commercial temperature range (0% to +70X) and Vcc supply voltage range of 4.75V-5.25V. At lower Vcc voltage, the access time is 80ns (4.5V-5.5V).

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical lCCR current is 1 mA at 5V Vcc.

When either CE,# or CE,#, and RP# pins are at Vco,

the I,, CMOS standby mode is enabled. When the

RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t,,o,) is required from RP# switching high until outputs are valid. Likewise, the device has a wake

time (tPHEL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset and

the status register is cleared. The device is available in 56-Lead TSOP (Thin Small

Outline Package, 1.2 mm thick). Pinout is shown in

Figure 2.

Rev. 1.8

SHARP

LHF16K55

CE# WE#

OE%

RPX

WPX

A20 49 Ala A17 A16

vcc

4s A14 A13 A12

CE,,#

VPP

RP#

AQ 43

GND

A6 A5 % A3 A2 Al

2 3

5 6

a 9 10

11 12 13 14 15

16 17 18 19 20 21 22 23

24 25 26 27 28

Figure 1. Block Diagram

56 LEAD TSOP

STANDARD PINOUT

14mm x 20mm

TOP VIEW

WP# WE# OE# STS

DQts

DQ7 DQ14

%I DQ13 DQ5 DQ12

DQ4 vcc

GND DQll

Ei:,

DQa

vcc

DQ9 DQI DQs DQo

A0 BYTE# NC

Figure 2. TSOP 56-Lead Pinout (Normal Bend)

Rev. 1.8

SHARP

LHF16K55 5

elects 1 of 2048 word lines.

commands during CUI write cycles; outputs data during memory

ower-down mode. For alternate configurations of the

laces the device in xl 6 mode

or eraslng

NC 1 NO CONNECT: Lead is not internal connected; it may be driven or floated.

array

, and turns off the A

Rev.1.8

SHARP

2 PRINCIPLES OF OPERATION

The LH28F160!35T-L70A Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte

write and block configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings.

After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status register, query structure and identifier codes :an be accessed through the CUI independent of the VP, voltage. High voltage on VP, enables successful >lock erase, full chip erase, (multi) word/byte write lnd block lock-bit configuration. All functions associated with altering memory contenttilock

erase, full chip erase, (multi) word/byte write and Ilock lock-bit configuration, status, query and dentifier codes-are accessed via the CUI and verified through the status register.

lock-bit

LHF16K55 6

Commands are written using

standard nicroprocessor write timings. The CUI contents serve 1s input to the WSM, which controls the block erase,

ull chip erase, (multi) word/byte write and block lock-

Iit configuration. The internal algorithms are

egulated by the WSM, including pulse repetition, nternal verification, and margining of data. lddresses and data are internally latch during write :ycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs luery structure or outputs status register data.

nterface software that initiates and polls progress of

block erase, full chip erase, (multi) word/byte write nd block lock-bit configuration can be stored in any Ilock. This code is copied to and executed from

ystem RAM during flash memory updates. After

uccessful completion, reads are again possible via

ne Read Array command. Block erase suspend

illows system software to suspend a block erase to

ead or write data from any other block. Write suspend allows system software to suspend a (multi) vord/byte write to read data from any other flash nemory array location.

o7oooo

OGFFFF

06ooOO

05FFFF

o5oooo

04FFFF

o4mo

OBFFFF

030000,

OZFFFF

o2owo _

OlFFFF

o1ocoo.

OOFFFF

WOO00

64-Kbyte Block 7 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 6CKbyte Block 3

64-Kbyte Block 64-Kbyte Block 64LKbyte Block

Figure 3. Memory Map

6 5

Rev. 1.8

SHARP

LHF16K55

2.1 Data Protection

Depending on the application, the system designer

may choose to make the Vnp power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to VPPH1. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When Vpp~VppLK, altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides orotection from unwanted operations even when high voltage is applied to V,,. All write functions are disabled when Vcc is below the write lockout voltage v,,, or when RP# is at V,,. The device’s block

ocking capability provides additional protection from

nadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations.

memory contents cannot be

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory :onform to standard microprocessor bus cycles.

3.1 Read

nformation can be read from any block, identifier :odes, query structure, or status register independent )f the V,, voltage. RP# must be at V,,.

-he first task is to write the appropriate read mode :ommand (Read Array, Read Identifier Codes, Query jr Read Status Register) to the CUI. Upon initial levice power-up or after exit from deep power-down node, the device automatically resets to read array node. Five control pins dictate the data flow in and ut of the component: CE# (CE,#, CE,#), OE#, WE#, IP# and WP#. CEo#, CE,# and OE# must be driven

ctive to obtain data at the outputs. CE,#, CE,# is le device selection control, and when active enables ie selected memory device. OE# is the data output 3Qc-DQ,,) control and when active drives the elected memory data onto the I/O bus. WE# and tP# must be at V,,. Figure 17, 18 illustrates a read ycle.

3.2 Output Disable

With OE# at a logic-high level (VI,), the device outputs are disabled. Output pins DQc-DQ,, arc placed in a high-impedance state.

3.3 Standby

Either CE,# or CE,# at a logic-high level (V,,) place: the device in standby mode which substantial11 reduces device power consumption. DQc-DQ,, outputs ar_e placed in a high-impedance state independent of OE#. If deselected during bloc1 erase, full chip erase, (multi) word/byte write ant block lock-bit configuration, the device continue:

functioning, and consuming active power until the operation completes.

3.4 Deep Power-Down

RP# at V,, initiates the deep power-down mode. In read modes, RP#-low deselects the memory

places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tnHav is required after

return from power-down until initial memory access outputs are valid. After this wake$p interval, norma operation is restored. The GUI is reset to read array mode and status register is set to 80H.

During block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, RP#-low will abort the operation. STS remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (V,,) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not

occur because the flash memory may be providing

status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

Rev. 1.8

SHARI=

LHF16K55

,5 Read Identifier Codes Operation

ie read identifier codes operation outputs the anufacturer code, device code, block status codes r each block (see Figure 4). Using the manufacturer rd device codes, the system CPU can automatically atch the device with its proper algorithms. The sck status codes identify locked or unlocked block !tiing and erase completed or erase uncompleted ndition.

3.6 Query Operation

The query operation outputs the query structure.

Query database is stored in the 48Byte ROM. Query structure allows system software to gain critica,

information for controlling the flash component. Query structure are always presented on the lowestorder data output (DC&,-DQ,) only.

3.7 Write

Writing commands to the CUI enable reading oi device data and identifier codes. They also control inspection and clearing of the status register. When Vcc=Vcc,,2 and VPP=VPPH1, the CUI additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration.

The Block Erase command requires appropriate

command data and an address within the block to be erased. The Word/byte Write command requires the

command and address of the location to be written.

Set Block Lock-Bit command requires the command

and block address within the device (Block Lock) to be locked. The Clear Block Lock-Bits command

requires the command and address within the device.

‘igure 4. Device Identifier Code Memory Map

The CUI does not occupy an addressable memory location. It is written when WE# &rd CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the V,, voltage 2 V,,,,, Read operations from

the status register, identifier codes, query, or blocks

are enabled. Placing VppHl on V,, :enables

successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.

Rev. 1.8

SHARf=

Mode

Read

Output Disable

LHF16K55

Table 3. Bus Operations(BYTE#=V,,)

Notes 1 RP# 1 CE,,# 1 CE,# OE# 1 WE# I Address

12733

3 3

4 9

!L IIH-

“I,

v,,

“I,

v,, v,,

“I, “1,

ll!ll-

“IL

v,, v,,

“I, “IL

l!lH-

X X

“IL

V,, V,H V,&j V,w

“IL

“I,

1 Vpp 1 DQn.,5 I STS ] 1 X Dn,,r

X High Z X X

High Z X

X High Z High Z X Note 5 High Z

3,mg

NOTES:

1. Refer to DC Characteristics. When V,,<V,,,k,

2. X can be V,, or VrH for control pins and addresses, and V,,,, or VPPHt for V,,. See DC Characteristics for V,nLk and V,r+n voltages.

3. STS is V,, (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or

deep power-down mode.

4. RP# at GNDM.2” ensures the lowest deep power-down current.

5. See Section 4.2 for read identifier code data.

6. See Section 4.5 for query data.

7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when VPP=VPPH1 and Vcc=Vcc,,2.

8. Refer to Table 4 for valid D,, during a write operation.

9. Don’t use the timing both OE# and WE# are VI,.

“I,

L!k.

“IL

memory contents can be read, but not altere%f:

“I,

v,r

X Note 6 High Z X D,N X

.,--

Rev. 1.8

SHARP

LHF16K55

Table 4. Commanc .

Bus Cycles Notes

Command Read Array/Reset Read Identifier Codes

Al lternate Word/Byte Write Setup/Write Multi Word/Byte Write Setup/Confirm

Block Erase and (Multi) Word/byte Write Suspend Confirm and Block Erase and (Multi) Word/byte Write Resume Block Lock-Bit Set Setup/Confirm Block Lock-Bit Reset Setup/Confirm STS Confiauration Level-Mode for Erase and Write 1 2 1 I Write I X (RY/BY# Mode) STS Confiauration Pulse-Mode for Erase STS Configuration Pulse-Mode for Write STS Configuration Pulse-Mode for Erase and Write IOTES:

. BUS operations are defined in Table 3 and Table 3.1.

. X=Any valid address within the device.

IA=ldentifier Code Address: see Figure 4. QA=Query Offset Address. BA=Address within the block being erased or locked. WA=Address of memory location to be written.

. SRD=Data read from status register. See Table 14 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high

first).

ID=Data read from identifier codes.

QD=Data read from query database.

. Following the Read Identifier Codes command, read operations access manufacturer, device and block status

codes. See Section 4.2 for read identifier code data.

. If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts

to issue a block erase or (multi) word/byte write to a locked block while RP# is V,,.

. Either 40H or 1OH are recognized by the WSM as the byte write setup.

A block lock-bit can be set while WP# is V,,.

. WP# must be at V,, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block

lock-bits.

Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm

command ‘DOH’.

3. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.

Req’d

1 WI,., , ,\ , I.II ,

1 5 Write X BOH

2 8 Write

z vvnte A aan 2 2 Write X B8H

4 I Write I X 1 90H 1 Read 1

5,6

7 Write

1 Definitions(lO)

First Bus Cycle

VU) ( Ad&(*) 1 Data@) Ope#) ) AI

opt

ritn

1 Y 1 FFU I

Write Write

Write

Write X

WA WA

BA 2

10H

E8H

DOH 1 5 Write

I B8H I Write I X I OOH /

B8H Write b : X 02H

Second

Write WA WD Write

Write

vvrw A Ull-l

Write X 03H

I Bus Cycle ddr(*) Datat3)

4 ID

WA N-l

7.-

Rev. 1.8

SHARP

LHF16K55 11

4.1 Read Array Command 4.3 Read Status Register Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/byte Write Suspend command. The Read Array command functions

ndependently of the Vpp

VIH-

voltage and RP# must be

1.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the qead Identifier Codes command. Following the :ommand write, read cycles from addresses shown in 7gure 4 retrieve the manufacturer, device, block lock :onfiguration and block erase status (see Table 5 for dentifier code values). To terminate the operation, Nrite another valid command. Like the Read Array :ommand, the Read Identifier Codes command unctions independently of the V,, voltage and RP# nust be Vi,. Following the Read Identifier Codes :ommand, the following information can be read:

Table 5. Identifier Codes

Code

Manufacture Code Device Code

Block Status Code

1 Address 1 Data 1 I nr\nnn

““““”

nnnn 1

The status register may be read to determine when i block erase, full chip erase, (multi) word/byte write OI block lock-bit configuration is complete and whethel the operation completed successfully(see Table 14) It may be read at any time by writing the Read Statu$ Register command. After writing this command, al

subsequent read operations output data from the status register until another valid command is written The status register contents are latched on the fallin< edge of OE# or CE#(Either CEc# or CE,#) whichever eccurs. OE# or CE#(Either CE,# or CE,#:

must toggle to VrH before further reads to update the status register latch. The Read Status Register command functions independently of the V,, voltage RP# must be V,,.

The extended status register may be read tc determine multi word/byte write availability(see Table

14.1). The extended status register may be read ai any time by writing the Multi Word/Byte Writs

command. After writing this command, all subsequeni

read operations output data from the extended status

update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.l are set to “1”s by the WSM and can only be reset by the

Clear Status Register command. These bits indicate various failure conditions (see Table 14). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking

multiple blocks or writing several bytes in sequence)

may be performed. The status register may be polled to determine if an error occurs during the sequence.

*Last erase operation did

not completed successfully

*Reserved for Future Use

IOTE:

X selects the specific block status code to be

read. See Figure 4 for the device identifier code memory map.

DC!,=1

DQ?-,

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V,, Voltage. RP# must be V,,. This command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bii configuration, block erase suspend or (multi) word/byte write suspend modes.

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1.5 Query Command

Juery database can be read by writing Query :ommand (98H). Following the command write, read ycle from address shown in Table 7-11 retrieve the xitical information to write, erase and otherwise :ontrol the flash component. A, of query offset tddress is ignored when X8 mode (BYTE#=V,L).

Juery data are always presented on the low-byte fata output (D&JDQ,). In x16 mode, high-byte

DQs-DQ,,) outputs OOH. The bytes not assigned to iny information or reserved for future use are set to 0”. This command functions independently of the Ipp voltage. RP# must be V,,.

Table 6. Example of Query Structure Output

Mode Off set Address

A,, A,, A,, A2, A, t A,

1 , 0 , 0 , 0 , 0 , 0 (20H) High-Z

X8mode 1 ,O,O,O,O,l (21H) High-Z

1, O,O,O,l ,0(22H) High-Z 1 , 0 , 0 , 0 , 1 , 1 (23H) High-Z “R”

Xl6 mode 1 , 0 , 0 , 0 , 0 (10H) OOH “0”

A,, A,, A,, A,,

l,O,O,O,l (11H) OOH “R”

output

DQ, q-~ DQ7-c

“Q” “Q” “R”

1.5.1 Block Status Register

-his field provides lock configuration and erase status for the specified block. These informations are only availabk vhen device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase statu. bit will be set to “1”. If bit 1 is “l”, this block is invalid.

Table 7. Query Block Status Register

Off set

(Word Address)

(BA+2)H OlH Block Status Register

lote:

. BA=The beginning of a Block Address.

Length

bit0 Block Lock Configuration

O=Block is unlocked l=Block is Locked

bit1 Block Erase Status

O=Last erase operation completed successfully

l=Last erase operation not completed successfully

bit2-7 reserved for future use

Description

%g.

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4.52 CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported.

Table 8. CFI Query Identification String

Offset

(Word Address)

lOH,l lH,l2H

13H,l4H 15H,l6H 17H,l8H lSH,lAH

Length

WH Query Unique ASCII strinq “QRY”

51 H,52H,59H

02H Primary Vendor Command Set and Control Interface ID Code

01 H,OOH (SCS ID Code)

02H Address for Primary Algorithm Extended Query Table

31 H,OOH (SCS Extended Query Table Offset)

02H Alternate Vendor Command Set and Control Interface ID Code

OOOOH (OOOOH means that no alternate exists)

02H Address for Alternate Algorithm Extended Query Table

OOOOH (OOOOH means that no alternate exists)

Description

4.5.3 System Interface Information

The following device information can be useful in optimizing system interface software.

Offset

(Word Address)

1BH 1CH 1DH

1EH

1FH 20H 21H 22H

23H

24H 25H 26H

Table 9. System Information String

Length Description

01H Vcc Logic Supply Minimum Write/Erase voltage

27H (2.7V)

OlH Vcc Logic Supply Maximum Write/Erase voltage

55H (5.5V)

OlH V,, Programming Supply Minimum Write/Erase voltage

27H (2.7V)

OlH V,, Programming Supply Maximum Write/Erase voltage

55H (5.5V)

OlH Typical Timeout per Single Byte/Word Write

03H (23=8us)

01H Typical Timeout for Maximum Size Buffer Write (32 Bytes)

06H (26=64us)

OlH Typical Timeout per Individual Block Erase

OAH (OAH=lO, 210=1024ms)

OlH

01H Maximum Timeout per Single Byte/Word Write, 2N times of typical. OlH Maximum Timeout Maximum Size Buffer Write, 2N times of typical. 01H 01H Maximum Timeout for Full Chip Erase, 2N times of typical.

Typical Timeout for Full Chip Erase OFH (OFH=15, 215=32768ms)

04H (24=1 6, 8usxl6=128us)

04H (24=1 6, 64usxl6=1024us)

Maximum Timeout per Individual Block Erase, 2N times of typical.

04H (24=1 6, 1024msx16=16384ms) 04H (24=1 6,32768msxl6=524288ms)

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4.5.4 Device Geometry Definition

This field provides critical details of the flash device geometry.

Table 10. Device Geometry Definition

Offset

(Word Address)

27H 01H Device Size

28H,29H 02H Flash Device Interface description 2AH,2BH 02H Maximum Number of Bytes in Multi word/byte write 2CH 2DH,2EH 1 02H 1 The Number of Erase Blocks

2FH,30H

Length

15H (15H=21, 22i=2097152=2M Bytes)

02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#)

05H,OOH (2s=32 Bytes )

OlH Number of Erase Block Regions within device

1 01 H (symmetrically blocked)

1 FH,OOH (1 FH=31 ==> 31 +1=32 Blocks)

02H The Number of “256 Bytes” cluster in a Erase block

OOH,Ol H (01 OOH=256 ==>256 Bytes x 256~ 64K Bytes in a Erase Block)

Description

1.5.5 SCS OEM Specific Extended Query Table

Zertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional rendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s).

Offset

(Word Address)

31 H,32H,33H 34H

35H 36H,37H, 38H,39H

3AH

3BH,3CH

3DH IEH

3FH

Table 11. SCS OEM Specific Extended Query Table

Length

03H PRI

50H,52H,49H OlH OlH 30H (0) Minor Version Number, ASCII 04H OFH,OOH,OOH,OOH

OlH OlH

02H 03H,OOH

OlH Vco Logic Supply Optimum Write/Erase voltage(highest performance) OlH V,, Programming Supply Optimum Write/Erase voltage(highest performance)

reserved Reserved for future versions of the SCS Specification

31H (1) Major Version Number, ASCII

Optional Command Support

bitO=l : Chip Erase Supported

bit1 =l : Suspend Erase Supported bit2=1 : Suspend Write Supported bit3=1 : LocWUnlock Supported bit4=0 : Queued Erase Not Supported bit531 =O : reserved for future use

Supported Functions after Suspend

bitO=l : Write Suooorted after Erase Susoend bit1 -7=O : reserved for future use

Block Status Register Mask

bitO=l : Block Status Register Lock Bit [BSR.O] active bitl=l : Block Status Register Valid Bit [BSR.l] active

bit2-15=0 : reserved for future use 50H(5.OV) 50H(5.OV)

Description

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