Philips f114 DATASHEETS
Philips Semiconductors Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with
common clock and reset inputs, features individual J, K, Clock (CP
Set (S
D) and Reset (RD) inputs, true and complementary outputs.
The S
D and RD inputs, when Low, set or reset the outputs as shown
in the Function Table regardless of the level at the other inputs.
A High level on the clock (CP
) input enables the J and K inputs and
data will be accepted. The logic levels and data will be accepted.
The logic levels at the J and K inputs may be allowed to change
while the CP
is High and flip-flop will perform according to the
Function Table as long as minimum setup and hold times are
observed. Output changes are initiated by the High-to-Low transition
of the CP
.
TYPICAL
TYPE
TYPICAL f
MAX
SUPPLY CURRENT
(TOTAL)
74F114 100MHz 15mA
),
74F1 14
PIN CONFIGURA TION
1
D
R
2
K0
3
J0
4
S
D0
5
Q0
6
Q
0
GND
ORDERING INFORMA TION
COMMERCIAL RANGE
= 5V ±10%,
DESCRIPTION
14-pin plastic DIP N74F114N SOT27-1
14-pin plastic SO N74F114D SOT108-1
V
CC
= 0°C to +70°C
T
amb
14
V
CC
13
CP
12
K1
11
J1
10
SD1
9
Q1
87
Q1
SF00110
PKG. DWG. #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
J0, J1 J inputs 1.0/1.0 20µA/0.6mA
K0, K1 K inputs 1.0/1.0 20µA/0.6mA
SD0, SD1 Set inputs (active Low) 1.0/5.0 20µA/3.0mA
RD Reset input (active Low) 1.0/10.0 20µA/6.0mA
CP Clock Pulse input (active falling edge) 1.0/8.0 20µA/4.8mA
Q0, Q0; Q1, Q1 Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
13
4
1
10
VCC = Pin 14
GND = Pin 7
SD0
RD0
SD1
CP
311
J1 K0
Q0 Q0
56
212
K1J0
Q1 Q1
98
SF00111
IEC/IEEE SYMBOL
1
13
4
3
2
10
11
12
R
C1
S
1K
1J
5
6
9
8
SF00112
1996 Mar 14 853–0340 16572
1
Philips Semiconductors Product specification
OPERATING MODE
Dual J-K negative edge-triggered flip-flop
with common clock and reset
LOGIC DIAGRAM
Q
S
D
K
CP
FUNCTION TABLE
INPUTS OUTPUTS
SD RD CP J K Q Q
L H X X X H L Asynchronous Set
H L X X X L H Asynchronous Reset
L L X X X H* H* Undetermined *
H H ↓ h l q q Toggle
H H ↓ l h L H Load “0” (Reset)
H H ↓ h l H L Load “1” (Set)
H H ↓ l l q q Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓ = High-to-Low clock transition
Asynchronous inputs: Low input to S
Set and Reset are independent of clock
Simultaneous Low on both S
* = Both outputs will be High while both S
D sets Q to High level, Low input to RD sets Q to Low level
D and RD makes both Q and Q High.
D and RD are Low, but the output states are unpredictable if S D and RD go High simultaneously.
TO OTHER
FLIP-FLOP
74F114
Q
RD
J
SF00113
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
1996 Mar 14
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 40 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
2
CC
V
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