Philips DVDR3305/05, DVDR3355/51, DVDR3355/05, DVDR3355/19, DVDR3365/02 Service Manual

Published by KC-TE 0530 AV Systems Printed in the Netherlands Subject to modifi cation EN 3139 785 30931

DVD-Video Recorder

CLASS 1

LASER PRODUCT

Contents Page

1 Technical Specifi cations and Connection
Facilities 2
2 Safety Information, General Notes & Lead
Free Requirements 5
3 Directions for Use 7
4 Mechanical Instructions 9
5 Upgrade Software & Repair Chart 12
6 Block Diagrams,Waveforms, Wiring Diagram 19
Overall block diagram 19
Control block diagram 20
Wiring diagram 21
Waveforms of Analog Board 22
Waveforms of Digital Board 23
Test Point Overview for Analog Board 24
Test Point Overview for Digital Board 25
7 Circuit Diagram and PWB Layout 26
Analog: Frontend Video (FV) 26
Analog: Video In / Out (IOV) 27
Analog: Audio In / Out (IOA) 28
Analog: Power Supply (PS) 29
Analog: Multi Sound Processing (MSP) 30
Analog: Audio Converter (DAC_ADC) 31
Analog: Digital In / Out 1 (DIGIO 1) 32
Layout: Analog-Main Part (Top View) 33
Layout: Analog-Main Part (Bottom View) 34
Front: Front Panel 35

Contents Page

Front: Front Panel 36
Layout: Front Panel (Top View) 37
Front: Standby 38
Layout: Standby (Top View) 38
Digital: Back-end Processor 39
Digital: Memory 40
Digital: IEEE 1394 Physical Layer 41
Digital: Video Input Processor 42
Digital: Interfaces 43
Layout: Digital-Main Part (Top View) 44
Layout: Digital-Main Part (Bottom View) 45
8 Circuit- and IC Description 47
Front Board (Panel – Display + Key) 47
Analog Board 47
Digital Board 52
IC Description 55
Analog Board 55
Digital Board 60
9 Exploded View & Spare Parts List 71
Exploded View of the set 71
Spare Parts List 72
10 Revision List 73

©

Copyright 2005 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.

Version 1.1

DVDR3305/02/05/19/51

Back End Repair

DVDR3355/02/05/19/51 & DVDR3365/02/05/19/51

EN 2

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1.

Technical Specifi cations and Connection Facilities

1. Technical Specifi cations and Connection Facilities

1.1 PCB Locations

1.2 General:

Mains voltage : 220V – 240V
Mains frequency : 50 Hz
Power consumption (typical) : 25 W
Standby Power Consumption : < 4 W

1.3 RF Tuner

Test equipment: Fluke 54200 TV Signal generator
Test streams: PAL BG Philips Standard test pattern

1.3.1 System

PAL B/G, PAL D/K, SECAM L/L’, PAL I

1.3.2 RF - Loop Through:

Frequency range : 45 MHz – 860 MHz
Gain: (ANT IN - ANT OUT) : -6dB to 0dB

1.3.3 Receiver:

PLL tuning with AFC for optimum reception
Frequency range : 45.25 MHz – 857 MHz
Sensitivity at 40dB S/N :  60dBV at 75 
(video unweighted)

1.3.4 Video Performance:

Channel 25 / 503,25 MHz,
Test pattern: PAL BG PHILIPS standard test pattern,
RF Level 74dBV
Measured on SCART 1
Frequency response : 0.1 – 4.00 MHz ± 3dB
Group delay (0.1 MHz - 4.4 MHz) : 0 nsec ± 150 nsec

1.3.5 Audio Performance:

Audio Performance Analogue - HiFi:

Frequency response at SCART 1
(L+R) output : 100 Hz – 12 kHz / 0 ±

3dB
S/N according to DIN 45405, 7, 1967
and PHILIPS standard test pattern
video signal :  50dB, unweighted
Harmonic distortion (1 kHz, ± 25
kHz deviation) :  1.5%

Audio Performance NICAM:
Frequency response at SCART 1
(L+R) output : 40 Hz – 15 kHz / 0 ±

3dB
S/N according to DIN 45405,7,1967
and PHILIPS standard test pattern
video signal :  60dB, unweighted
Harmonic distortion (1kHz) :  0.5%

Front boards

(Behind the

metal bracket)

Digital Board

Basic Engine

Analog Board

EN 3

3139 785 3093x

1.

Technical Specifi cations and Connection Facilities

1.3.6 Tuning

Automatic Search Tuning

Scanning time without antenna : typ. 3 min.
Stop level (vision carrier) :  37dBV
Maximum tuning error of a recalled
program : ± 62.5 kHz
Maximum tuning error during
operation : ± 100 kHz

Tuning Principle

Automatic B, G, I, DK and L/L’ detection
Manual selection in “STORE” mode

1.4 Analogue Inputs / Outputs

1.4.1 SCART 1 (Connected to TV)

Pin Signals:

1 - Audio R 1.8V RMS
2 - Audio R
3 - Audio L 1.8V RMS
4 - Audio GND
5 - Blue / GND
6 - Audio L
7 - Blue out
8 - Function switch < 2V = TV
> 4.5V / < 7V = asp. Ratio 16:9 DVD
> 9.5V / < 12V = asp. Ratio 4:3 DVD
9 - Green GND
10 - NC
11 - Green 0.7Vpp ± 0.1V into 75 (*)
12 - NC
13 - Red GND
14 - Fast switch GND
15 - Red out 0.7Vpp ± 0.1V into 75 (*)
16 - Fast switch
RGB / CVBS < 0.4V into 75 = CVBS
>1V / < 3V into 75 = RGB
17 - CVBS GND OUT
18 - CVBS GND IN
19 - CVBS out 1Vpp ± 0.1V into 75 (*)
20 - CVBS in
21 - Shield

1.4.2 SCART 2 (Connected to AUX)

Pin Signals:

1 - Audio R 1.8V RMS
2 - Audio R
3 - Audio L 1.8V RMS
4 - Audio GND
5 - Blue GND
6 - Audio L
7 - Blue in
8 - Function switch
9 - Green GND
10 - NC
11 - Green in
12 - NC
13 - Red GND
14 - Fast switch GND
15 - Red in
16 - Fast switch
RGB / CVBS
17 - CVBS GND OUT
18 - CVBS GND IN
19 - CVBS / RGB
out sync 1Vpp ± 0.1V into 75 (*)
20 - CVBS in
21 - Shield

(*) for 100% white

1.4.3 Audio/Video Front Input Connectors

Audio - Cinch

Input voltage : 2.2Vrms
Input impedance : > 10k

Video - Cinch

Input voltage : 1Vpp ± 3dB
Input impedance : 75

Video - YC (Hosiden)

According to IEC 933-5
Superimposed DC-level on pin 4 (load > 100k)
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio
Input voltage Y : 1Vpp ± 3dB
Input impedance Y : 75
Input voltage C : burst 300mVpp ± 3dB
Input impedance C : 75

1.4.4 Audio/Video Output rear Connectors

Audio - Cinch

Output voltage : 2Vrms max.
Output impedance : > 10k

Video - Cinch

Output voltage : 1Vpp ± 3dB
Output impedance : 75

Video - YC (Hosiden)

According to IEC 933-5
Superimposed DC-level on pin 4 (load > 100k)
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio
Output voltage Y : 1Vpp ± 10/-15%
Output voltage C : 300mVpp ± 1/-4dB

1.5 Video Performance

All outputs loaded with 75 
SNR measurements over full bandwidth without weighting.

1.5.1 SCART (RGB)

SNR : > -65dB on all output
Bandwidth : 4.8MHz ± 2dB

1.6 Audio Performance CD

1.6.1 Cinch Output Rear

Output voltage 2 channel mode : 2Vrms ± 2dB
Channel unbalance (1kHz) : < 1dB
Crosstalk 1kHz : > 95dB
Crosstalk 16Hz-20kHz : > 87dB
Frequency response 20Hz-20kHz : ± 0.2dB max
Signal to noise ratio : > 85dB
Dynamic range 1kHz : > 83dB
Distortion and noise 1kHz : > 83dB
Distortion and noise 16Hz-20kHz : > 75dB
Intermodulation distortion : > 70dB
Mute : > 95dB
Outband attenuation: : > 40dB above 30kHz

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1.

Technical Specifi cations and Connection Facilities

1.6.2 Scart Audio

Output voltage 2 channel mode : 1.6Vrms ± 2dB
Channel unbalance (1kHz) : < 1dB
Crosstalk 1kHz : > 85dB
Crosstalk 16Hz-20kHz : > 70dB
Frequency response 20Hz-20kHz : ± 0.2dB max
Signal to noise ratio : > 80dB
Dynamic range 1kHz : > 75dB
Distortion and noise 1kHz : > 75dB
Distortion and noise 16Hz-20kHz : > 50dB
Intermodulation distortion : > 70dB
Mute : > 80dB
Outband attenuation: : > 40dB above 25kHz

1.7 Digital Output

1.7.1 Coaxial

CDDA / LPCM (incl MPEG1) : according IEC958,

IEC60958-1,-3

MPEG2, AC3 audio : according IEC1937,

IEC61937

DTS : according IEC1937,

IEC 61937
amendment 1

1.8 Digital Video Input (IEEE 1394)

1.8.1 Applicable Standards

Implementation according:
IEEE Std 1394-1995
IEC 61883 - Part 1
IEC 61883 - Part 2 SD-DVCR (02-01-1997)

Specifi cation of consumer use digital VCR’s using 6.3 mm
magnetic tape - dec. 1994
Annex A of 61883-1

1.9 Dimensions and Weight

Height of feet : 5.5mm
Apparatus tray closed : WxDxH:435x285x65mm
Apparatus tray open : WxDxH:435x422x65mm
Weight without packaging : app. 4.0kg ± 0.5kg
Weight with packaging : app. 6kg

1.10 Laser Output Power & Wavelength

1.10.1 DVD

Output power during reading : 0.8mW
Output power during writing : 20mW
Wavelength : 660nm

1.10.2 CD

Output power : 0.3mW
Wavelength : 780nm

EN 5

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2.

Safety Information, General Notes & Lead Free Requirements

2.1 Safety Instructions

2.1.1 General Safety

Safety regulations require that during a repair:

• Connect the unit to the mains via an isolation transformer.

• Replace safety components, indicated by the symbol ,
only by components identical to the original ones. Any
other component substitution (other than original type)
may increase risk of fi re or electrical shock hazard.

Safety regulations require that after a repair, you must return
the unit in its original condition. Pay, in particular, attention to
the following points:

• Route the wires/cables correctly, and fi x them with the
mounted cable clamps.

• Check the insulation of the mains lead for external
damage.

• Check the electrical DC resistance between the mains
plug and the secondary side:

1. Unplug the mains cord, and connect a wire between
the two pins of the mains plug.

2. Set the mains switch to the ‘on’ position (keep the
mains cord unplugged!).

3. Measure the resistance value between the mains
plug and the front panel, controls, and chassis
bottom.

4. Repair or correct unit when the resistance
measurement is less than 1 M.

5. Verify this, before you return the unit to the customer/
user (ref. UL-standard no. 1492).

6. Switch the unit ‘off’, and remove the wire between the
two pins of the mains plug.

2.1.2 Laser Safety

This unit employs a laser. Only qualifi ed service personnel
may remove the cover, or attempt to service this device (due
to possible eye injury).

Laser Device Unit

Type : Semiconductor laser
GaAlAs
Wavelength : 650 nm (DVD)
: 780 nm (VCD/CD)
Output Power : 20 mW
(DVD+RW writing)
: 0.8 mW
(DVD reading)
: 0.3 mW
(VCD/CD reading)
Beam divergence : 60 degree

CLASS 1

LASER PRODUCT

Figure 2-1

Note: Use of controls or adjustments or performance of
procedure other than those specifi ed herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.

2.2 Warnings

2.2.1 General

• All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD, ). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are at the same potential as the mass
of the set by a wristband with resistance. Keep
components and tools at this same potential.
Available ESD protection equipment:
– Complete kit ESD3 (small tablemat, wristband,
connection box, extension cable and earth cable)
4822 310 10671.
– Wristband tester 4822 344 13999.

• Be careful during measurements in the live voltage
section. The primary side of the power supply, including
the heatsink, carries live mains voltage when you
connect the player to the mains (even when the
player is ‘off’!). It is possible to touch copper tracks and/
or components in this unshielded primary area, when
you service the player. Service personnel must take
precautions to prevent touching this area or components
in this area. A ‘lightning stroke’ and a stripe-marked
printing on the printed wiring board, indicate the primary
side of the power supply.

• Never replace modules, or components, while the unit is
‘on’.

2.2.2 Laser

• The use of optical instruments with this product, will
increase eye hazard.

• Only qualifi ed service personnel may remove the cover or
attempt to service this device, due to possible eye injury.

• Repair handling should take place as much as possible
with a disc loaded inside the player.

• Text below is placed inside the unit, on the laser cover
shield:

Figure 2-2

2.2.3 Notes

Dolby

Manufactured under licence from Dolby Laboratories. “Dolby”,
“Pro Logic” and the double-D symbol are trademarks of Dolby
Laboratories. Confi dential Unpublished Works.
©1992-1997 Dolby Laboratories, Inc. All rights reserved.

Figure 2-3

Trusurround

TRUSURROUND, SRS and symbol (fi g 2-4) are trademarks
of SRS Labs, Inc. TRUSURROUND technology is
manufactured under licence frm SRS labs, Inc.

Figure 2-4

2. Safety Information, General Notes & Lead Free Requirements

CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO ! AVATTAESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS D’OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU

EN 6

3139 785 3093x

2.

Safety Information, General Notes & Lead Free Requirements

Video Plus

“Video Plus+” and “PlusCode” are registered trademarks of
the Gemstar Development Corporation. The “Video Plus+”
system is manufactured under licence from the Gemstar
Development Corporation.

Figure 2-5

Macrovision

This product incorporates copyright protection technology that
is protected by method claims of certain U.S. patents and
other intellectual property rights owned by Macrovision
Corporation and other rights owners.
Use of this copyright protection technology must be
authorized by Macrovision Corporation, and is intended for
home and other limited viewing uses only unless otherwise
authorized by Macrovision Corporation. Reverse engineering
or disassembly is prohibited.

2.3 Lead Free Requirement

Information about Lead-free produced sets

Philips CE is starting production of lead-free sets from

1.1.2005 onwards.

INDENTIFICATION:

Regardless of special logo (not always indicated)

One must treat all sets from 1 Jan 2005 onwards, according
next rules.

Example S/N:

Bottom line of typeplate gives a 14-digit S/N. Digit 5&6 is the year, digit 7&8 is
the week number, so in this case 1991 wk 18

So from 0501 onwards = from 1 Jan 2005 onwards

Important note: In fact also products of year 2004 must be treated in this way as long as you
avoid mixing solder-alloys (leaded/ lead-free). So best to always use SAC305 and the higher
temperatures belong to this.

Due to lead-free technology some rules have to be respected by the
workshop during a repair:

• Use only lead-free solder alloy Philips SAC305 with order

code 0622 149 00106. If lead-free solder-pate is required,

please contact the manufacturer of your solder-equipment.

In general use of solder-paste within workshops should be

avoided because paste is not easy to store and to handle.

• Use only adequate solder tools applicable for lead-free

solder alloy. The solder tool must be able
o To reach at least a solder-temperature of 400°C,
o To stabilize the adjusted temperature at the solder-tip
o To exchange solder-tips for different applications.

• Adjust your solder tool so that a temperature around 360°C

– 380°C is reached and stabilized at the solder joint.

Heating-time of the solder-joint should not exceed ~ 4 sec.

Avoid temperatures above 400°C otherwise wear-out of tips

will rise drastically and fl ux-fl uid will be destroyed. To avoid

wear-out of tips switch off un-used equipment, or reduce

heat.

• Mix of lead-free solder alloy / parts with leaded solder alloy

/ parts is possible but PHILIPS recommends strongly to

avoid mixed solder alloy types (leaded and lead-free).

If one cannot avoid or does not know whether product is

lead-free, clean carefully the solder-joint from old solder

alloy and re-solder with new solder alloy (SAC305).

• Use only original spare-parts listed in the Service-Manuals.

Not listed standard-material (commodities) has to be

purchased at external companies.

• Special information for BGA-ICs:

- always use the 12nc-recognizable soldering temperature

profi le of the specifi c BGA (for de-soldering always use the

lead-free temperature profi le, in case of doubt)

- lead free BGA-ICs will be delivered in so-called ‘dry-

packaging’ (sealed pack including a silica gel pack) to

protect the IC against moisture. After opening, dependent

of MSL-level seen on indicator-label in the bag, the

BGA-IC possibly still has to be baked dry. (MSL=Moisture

Sensitivity Level). This will be communicated via AYS-

website.
Do not re-use BGAs at all.

• For sets produced before 1.1.2005 (except products of

2004), containing leaded solder-alloy and components,

all needed spare-parts will be available till the end of the

service-period. For repair of such sets nothing changes.

• On our website www.atyourservice.ce.Philips.com you

fi nd more information to:

 BGA-de-/soldering (+ baking instructions)
 Heating-profi les of BGAs and other ICs used in Philips-sets

You will fi nd this and more technical information within the

“magazine”, chapter “workshop news”.

For additional questions please contact your local repair-helpdesk.

EN 7

3139 785 3093x

3.

Directions For Use

3. Directions For Use

The following except of the Quick Use Guide serves as an introduction to the set.
The Complete Direction for the Use can be downloaded in different languages from the internet site of Philips Customer care Center:

www.p4c.philips.com

QUICK START GUIDE

12nc: 3139 246 15861

DVDR3365

1 what’s in the box

2 connect DVD recorder

A

Main Unit

RF coaxial
cable

C

D

includes 2x AA batteries

Scart cable

B

Remote
Control

2a Connect existing antenna cable/satellite signal (or from

the Cable/Satellite Box [RF OUT or TO TV]) to the

ANTENNA

input socket at the back of the DVD

recorder.

2b Use the supplied RF coaxial cable to connect the DVD

recorder’s TV output socket to your TV’s antenna
input socket.

2c Use the supplied Scart cable to connect the DVD

recorder’s EXT 1 TO TV-I/O socket to the matching
SCART input socket at the back of your TV.

2d Connect the power cable from the DVD recorder’s

~ MAINS to the AC power outlet.

Helpful Hint:
For additional connection diagrams, see User
Manual pages 12~19.

3 Start initial setup

DVD recorder back panel

2a

2b

2d

System Menu - Channel Setup

Modify Channel Information

Search

Edit

System Menu - Language

Default Disc Menu Language

Default Subtitle Language

On Screen Display Language

English

Default Audio Language

English

English

English

System Menu - Clock

Time (hh:mm:ss}

Show DivX® Registration Code

Date (dd/mm/yy)

31/01/05

10 : 33 : 57

OK

Sort Channel

Sort

Channel Search

System Menu - General

Video Output Format

Screen Saver

On

Restore Factory Settingd

Germany

PAL

OK

Country

3a Press STANDBY-ON 2 on

the DVD recorder to turn it on.

Note: For successful installation,
your cable/satellite box must be
turned on.

3b Turn on the TV to the correct

programme channel for the
input socket (‘EXT’, ‘0’, ‘AV’).

➜ The blue PHILIPS DVD

background screen will appear on
the TV.

3c Press SYSTEM MENU on the

remote control.

➜ Use 34 keys to go through the

menu. Select an item by pressing 2,
and confirm a setting by pressing

OK.

3d Highlight and press 2.

Select the country of your
residence..

Select { Country } and press OK
on the remote control.

3e Highlight and press 2.

Setup and install TV channels.

Select { Channel Search } and
press OK on the remote control
to start automatic TV channel
search.

3f Highlight and press 2.

Select the language.

– select TV On-Screen Display

language.
– select default Disc Menu language.
– select default subtitle language.
– select default audio language.

3g Highlight and press 2.

Set the Date and Time.

Use the numeric keypad 0-9 to
input the date/time, then press OK
to confirm.

3h Press SYSTEM MENU to exit.

The DVD recorder is ready for use!

See next page for basic recording and playback.

2c

EN 8

3139 785 3093x

4 start manual recording

5 start playback

NEED HELP? Read the accompanying User Manual or visit our website www.philips.com/support

To playback a disc

5a Insert a disc with the label side

facing up.

5b Playback may start automatically.

If not, press PLAY 2.

➜ If a disc menu appears,

use 1234 keys to navigate
within the menu, highlight a title and
press OK to start playback.

5c To stop playback, press

STOP9.

To watch the TV
programmes

5d Press REC SOURCE to select

{ Tuner }, then use 34 keys to
select the programme number.

GET SOUND

•

Use the supplied scart cable to connect the DVD recorder to
your TV, the picture and sound will output through the TV.

• Or, connect the AUDIO L/R (red/white) sockets at the back of the

DVD recorder to the corresponding AUDIO input sockets on a
TV, stereo system or receiver. Turn on the connected system and
select the appropriate channel.

GET PICTURE

• Check the AV mode on TV. It may be called FRONT, A/V IN, or

VIDEO. Choose the different modes using TV remote control.

• Or, use the TV remote control to select Channel 1 on TV, then

press Channel down button until you get the picture.

• See your TV manual for more details.

4a Insert a recordable

DVD+R/+RW with the label
facing up.

4b To record TV programme, press

REC SOURCE to select

{ Tuner }.

To record from an external
device connected to this DVD
Recorder, press REC SOURCE
repeatedly to select the
corresponding external input
channel : { Front CVBS }
{ Front S-Video }, { DV },
{ EXT 2 }.

4c Press REC MODE to select a

desired recording mode.
It defines the picture quality and
the maximum recording time
for a disc.

4d Press REC 0 to start recording.

4e To pause the recording, press ;.

To resume recording,
press REC 0.

To stop the recording, press
STOP 9.

➜ Wait until the message

disappears from the display panel
before you remove the disc.

SUPER VIDEO

Record

Mode

Picture Quality

Maximum Recording

Time per Disc

1 Hour Mode

2 Hour Mode

4 Hour Mode

6 Hour Mode

High quality

DVD quality-Standard Play

VHS quality-Extended Play

VHS quality-Super Long Play

1 hour

2 hours

4 hours

6 hours

3.

Directions For Use

EN 9

3139 785 3093x

4.

Mechanical Instructions

4. Mechanical Instructions

4.1 Dismantling and Assembly of the Set

For item numbers please see the exploded view in Chapter 9.

4.1.1 Dismantling of the DVD Loader Tray Cover

1) Inserting a minus screw driver and push the lever in the
direction as shown in Figure 4-1 to unlock the tray before
sliding it out.

Figure 4-1

2) Remove the Tray Cover as shown in Figure 4-2.

Figure 4-2

4.1.2 Dismantling of the Front Panel Assembly

1) Remove the 3 screws 188 and release the 2 snap hooks
on the side before removing the front assembly.

1

Figure 4-3

2) Remove the 5 screws 186 to remove the front plate 184
as shown in Figure 4-4.

2

2

Figure 4-4

EN 10

3139 785 3093x

4.

Mechanical Instructions

4.1.3 Dismantling of the Basic Engine

1) Remove the Cover Tray (See 4.1.1).

2) Remove the 4 screws 260 to free the Basic Engine.

3

3

Figure 4-5

3) Place the Basic Engine in the service position by fl ipping
the basic engine to the vertical position

Figure 4-6

4.1.4 Dismantling of the Digital Board

1) Remove the 4 screws 272 to loose the Digital Board as
shown in Figure 4-7.

4

4

Figure 4-7

2) Service Position can be achieved by fl ipping the Digital
board to the Vertical Position as shown in Figure 4-8.

Figure 4-8

Note: The cable (just to transfer the service connection to the

analog board) from socket 1101 can be removed and use for
hyperterminal connection.

EN 11

3139 785 3093x

4.

Mechanical Instructions

4.1.5 Dismantling of the Analog Board

1) Remove 5 screws 244 and 4 screws 252 and screw 230.

2) Remove 4 screws 270 and 3 screws 268.

3) Service Position can be achieved by fl ipping the analog
board to the Vertical Position as shown in Figure 4-9.

Figure 4-9

Note: Please cover the Live Area during trouble-shooting.

(Figure 4-10)

Figure 4-10

Figure Live Area

EN 12

3139 785 3093x

5.

Upgrade Software & Repair Chart

5. Upgrade Software & Repair Chart

5.1 Upgrade Software

A. Preparation to upgrade fi rmware:

1. Unzip the zip-archive fi le

2. Start the CD Burning software and create a new CD
project (data disc) with the following settings:
File system : Joliet
Format : MODE 1: CDROM
Recording mode : SINGLE SESSION (TRACK­ AT-ONCE), FINALIZED CD

Note: Long fi le name is necessary for the preparation of
the upgrade disc

3. Place the content of the zip-archive into the root directory
of the new CD project.

4. Burn the data onto a blank CDR or CD-RW

B. Procedure to apply the fi rmware upgrade:

1. Power up the set and open tray.

2. Insert the prepared Upgrade CDROM and close the tray.

3. The TV connected to the set will display:

Software Upgrade Disc detected

Select OK to start or CANCEL to exit

4. Select OK or CANCEL with the <Right> or <Left> button
and press <OK> button to confi rm.

5. The TV connected to the set will display:

Upgrading Software, Please wait

Do not switch off the power

6. When the upgrading process is successful the tray will
open and the TV connected to the set will display:

System is successfully upgraded.

Remove disc from tray & reset system

7. Remove the Upgrade Disc and press <OK> button on
Remote control to confi rm

8. The TV screen goes blank and the Philips Logo screen
appear again after the tray door has closed.

C. How to Restore Factory setting (Default
setting)

1. Power up the set and with no disc in the tray

2. Press <System Menu> <Right> and 4x <Down> buttons
on the Remote control to reach the Restore Factory
setting option.

3. Press <OK> button and the TV connected to the set will
display:

System will reset to the Factory settings.

Select OK to confi rm or CANCEL to exit.

4. Select OK or CANCEL with the <Right> or <Left> button
and press <OK> button to confi rm.

Note: All customers’ settings will be lost.

D. How to read out the fi rmware version to
confi rm set has been upgraded.

1. Power up the set and with no disc in the tray

2. Press <0009> and <OK> buttons on the Remote control

3. The TV connected to the set will display:

DVDR3365_75_BT3_2, Drive: 43.02.11 Build:

FAE6206 Apr 21 2005, 18:49:43

where DVDR3365_75 = Type/version
BT3_2 = Application (Backend) fi rmware
version

43.02.11 = Drive (Basic Engine) fi rmware
version

EN 13

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2 Repair Chart

5.2.1 Completely Dead Set

EN 14

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2.2 Cannot Read Disk

5.2.3 Disk Unknown

EN 15

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2.4 Audio No Sound (Playback)

EN 16

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2.5 Audio No Sound (TV & External Source)

EN 17

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2.6 No Video Out Upon Power ON (Assume set is not dead)

EN 18

3139 785 3093x

5.

Upgrade Software & Repair Chart

5.2.7 No Video In Only

5.2.8 Tuner Not Functioning

EN 19

3139 785 3093x

6.

6. Block Diagrams, Waveforms, Wiring Diagram

Block Diagrams, Waveforms, Wiring Diagram.

Overall Block Diagram of the Set

Front Keyboards

Digital Video
Input IEEE1394

CVBS-YUV-Y/C

AUDIO PCM I2S

A_BCLK

A_WCLK

A_DATA

SPDIF_OUT

D_KILL

AUDIO ENCODER I2S

YUV-YC-CVBS

ANALOG AUDIO / VIDEO

D_CVBS

D_C

D_Y

D_V

D_Y1

D_U

A_V

A_U

A_Y

A_C

TUNER

INPUT/OUTPUT
PROCESSING &
SOURCE
SELECTION

ANALOG BOARD

MAINS
AC

F439

F440

F441

F442

F443

F444

2

1

AFCRI

AFCLI

CVBSFIN

CFIN

YFIN

3

4

5

7

9

1922

1201

1512

1204

1205

1600

1536

S-VIDEO

CVBS

AUDIO R

AUDIO L

AINFR

AINFL

CVBSFIN

CFIN

YFIN

ADC

7
9

11

12

13

14

15

12

14

16

18

20

22

DDRAM

FLASH

VIDEO INPUT
PROCESSING

DIGITAL AUDIO

RS232

SERVICE

1111

1522

1551

DIG.VIDEO

21
20

18

2

16

7

1

3

5

7

9

RF IN - ANTENNA

RF OUT - TV

PHY

F438

DIGITAL AUDIO OUT

DOMINO DMN-8602

MPEG 2, AC3 CODEC

EEPROM

DIGITAL AUDIO

I2C

A_PCMCLK

A_xCLK

BUFFER

A_YCVBS

DA C

D_DATA0

D_WCLK

D_BCLK

9

11

12

14

D_PCMCLK

D_xCLK

ANALOG VIDEO

1800

POWER
SUPPLY

PSU

5N

GND5VGND

GND

12V

GND

3V3

3V3

3V3

3V3

1403

1

12

-5V

GND

ION

+5V

GND

GND

+12V

GND

+3V3

+3V3

+3V3

+3V3

1501

1

12

CONTROL LINES

CONTR

OL LINES SCK,D_FM,D_HOST,RDY_FM,ATN_FM,HOST_RESET

IDE BUS

FAN

1804

6

IDE BUS

1934

DIGITAL BOARD - DIMENSION

DVD+RW ENGINE D4.3

TRAY CONTROL

SERVO

READ

WRITE

DISC

PSU

40

LASER

1600-1

+5V

GND

GND

+12V

1600-2

1571

CONTROL LINES, AND SUPPLY LINES

1803

(LOOP THROUGH)

CONTROL UNIT SLAVE

MICROPROCESSOR

VPD 16316GB-006

For Digital Video version only

(OPTION)

(OPTION)

S-VIDEO

CVBS

AUDIO L/R

2

1

21

19

EXT1

TV-I/O

2

1

21

19

EXT2

AUX-I/O

A/V OUT

EN 20

3139 785 3093x

6.Block Diagrams, Waveforms, Wiring Diagram.

Control Block Diagram Analog Board

Frontend

Tuner

I2C Bus

Repeater

ASP Analog Slave Processor

NEC uPD-16316GBT

Audio Switches

HEF4052B

Fan

>=1

Reset

Multi Sound

Processor
MSP34x5

>=1

KILL

Supply

VFT

Display

Powe r
Supply

RC

Fron t
Keys

DIGITAL BOARD DIMENSION

DVD R

D_KILL

AIN_SEL0, AIN_SEL1

IDE0

HOST_Reset

I2C

5V

INT

I2C
3V3

Reset

5VSTBY

2

2

2

1

1

35

STBY

POWER_FAIL

BKILL

>=1

KILL

AKILL

RSA1,RSA2

FRONT Board

FAN_CTRL

Control Block Diagram

EN 21

3139 785 3093x

6.

Block Diagrams, Waveforms, Wiring Diagram.

Wiring Diagram

Interconnection Diagram Architecture

FRONT PCB

MAINS AIO COM VIO KB_FC FAN KB_FC

CORD 1600 1800 1205 1206 1802 1803 1201

1 MAINS P 22

GND

20 GND 30 A_YG

14

GND 1 FAN_P

14

GND

2 MAINS L 21

DAOUT

19 SCL0 29 GNDV

13

SCK 2 FAN_N

13

SCK

20

GND

18 SDA0 28 A_UB

12

D_FM

12

D_FM

19

DAINOPT

17

RDY_FM

27 GNDV

11

D_HOST

11

D_HOST

18

NO_CONNECT16D_FM

26 A_VR

10

GND

10

GND

17

DAINCOAX

15

D_HOST

25 GNDV

9

RDY_FM

9

RDY_FM

16

MUTE

14 GND

24

24 Y_FIN

8

ATN_FM

8

ATN_FM

PDUDIG

15

GND

13

SCK 23

23 GNDV

7

HOST_RESET

7

HOST_RESET

1401

14

D_PCMCLK

12 ATN_FM

22

22 C_FIN

6

RC_IN

IPFAI

L

6

RC_IN

13

GND

11 HOST_RESET

21

21 CVBS_FIN

5

5VSTBY

1205

5

5VSTBY

1 3V3 12

D_DATA0

10

CVBS_Y SW 20

20 GNDV

4

STBY(POWER_CTRL)1YFIN

4

STBY(POWER_C

2 3V3 11

D_WLCK

9

AIN_SEL0 19

19 C_REAR

3

IPFAIL

2

GND

3

IPFAIL

3 3V3 10

GND

8

AIN_SEL1 18

18 GNDV

2

VGNSTBY

3

CFIN

2

VGNSTBY

4 12VEF 9

D_BLCK

7

TU_DET 17

17 Y_REAR

1

12VSTBY

4

GND

1

12VSTBY

5GND 8

GND

6

FAN CTRL 16

16 GNDV

5

CVBS_FIN

612

V

7

A

_PCMCL

K

5

FBIN 15

15 CVBS_REA

R

PSUDRIVE

6

GND

FA

V

7GND 6

GND

4

SC 2 pin 8_1 14

14 GNDV

1402

7

AL_FIN

1300

8GND 5

A_DATA

3

SC 2 pin 8_2 13

13 CVBS_TU

8

GND

1

YFIN

95V 4

GND

2

RC 12

12 GNDV 1 12VE

9

AINFR

2

GND

10 5V 3

A_WCLK

1GND

11

11 D_CVBS 2 GND

3

CFIN

11 GND 2

A_BCLK 10

10 GNDV 3 GND

4

GND

12 5N 1

GND 9

9D_C 4 5VE

5

CVBS_FIN

88

GNDV

ANALOG BOARD

6

GND

77

D_Y

7

AL_FIN

66

GNDV

8

GND

55

D_VR

9

AR_FIN

44

GNDV

33

D_YG

2 2 GNDV
1 1 D_UB

Front Drive
DV-In PSUDRIVE

JST LC

1 12VE
2 GND
3 GND
4 5VE

USB
1401/1402

1 5VUSB1
2 USB1_D+

PSDIG AIO COM VIO IDE_ IDE_ 3 USB1_D-
1501 1536 1551 1522 1521 1571 4 GND

1 3V3 1 GND 1 GND 30 VIA_GY

1 RESETn

1 RESETn

2 3V3 2 BCKI 2 SCL0 29 GNDV

2

GND 2 GND

STDBY KEY

3 3V3 3 WCKI 3 SDA0 28 VIA_BPb

3

DD[7] 3 DD[7]

0100

4 3V3 4 GND 4 RDY_FM 27 GNDV

4

DD[8] 4 DD[8] 1 KEY1

5 GND 5 DAI (0) 5 D_FM 26 VIA_RPr

5

DD[6] 5 DD[6] 2 KEY2

6 12V 6 GND 6 D_HOST 25 GNDV

6

DD[9] 6 DD[9]

7 GND 7 MCKI 7 GND

24

24 VIA_SY_FR

7

DD[5] 7 DD[5]

8 GND 8 GND 8 FPSCK

23

23 GNDV

8

DD[10] 8 DD[10]

9 5V 9 BCKO 9 ATN_FM

22

22 VIA_SC_FR 9 DD[4] 9 DD[4]

10 5V 10 GND 10 HOST_RESET 21 21 VIA_CVBS_FR PH2mm 10 DD[11] 10 DD[11]
11 GND 11 WCKO 11 VIOSW 20 20 GNDV 1512 11 DD[3] 11 DD[3]
12 NC 12 DAO (0) 12 AIN_SEL0 19 19 VIA_SC_RE 12 DD[12] 12 DD[12]

13 GND 13 AIN_SEL1 18 18 GNDV 1 TPBn 13 DD[2] 13 DD[2]
14 MCKO 14 COM_ARST 17 17 VIA_SY_RE 2 TPB 14 DD[13] 14 DD[13]
15 GND 15 FAN CTRL 16 16 GNDV 3 GND 15 DD[1] 15 DD[1]
16 MUTE
17 NC
18 NC
19 NC

16 FBIN 15 15 VIA_CVBS_RE 4 TPAn 16 DD[14] 16 DD[14]
17
18
19

SBS0 14 14 GNDV 5 TPA 17 DD[0] 17 DD[0]
SBS 1 13 13 VIA_CVBS_TU 6 GND 18 DD[15] 18 DD[15]

FPIR 12 12 GNDV 19 GND 19 GND
20 GND 20 GND 11 11 VOA_CVBS 20 Keypin 20 Keypin
21 SPO 10 10 GNDV 21 DMARQ 21 DMARQ
22 GND 9 9 VOA_SC 22 GND 22 GND

8 8 GNDV 23 DIOW_n 23 DIOW_n
7 7 VOA_SY 24 GND 24 GND
6 6 GNDV 25 DIOR_n 25 DIOR_n
5 5 VOA_RPr 26 GND 26 GND
4 4 GNDV 27 IORDY 27 IORDY STDBY KEY
3

3

VOA_GY

USB 28 CSEL

28 CSEL

1302

2 2 GNDV 1502 29 DMACK_n 29 DMACK_n 1 KEY1

DIGITAL BOARD 1 1 VOA_BPb 1 5VUSB1 30 GND 30 GND 2 KEY2

2 USB1_D+ 31 INTRQ 31 INTRQ
3 USB1_D- 32 IOCS16 32 IOCS16
4 GND 33 DA1 33 DA1

34 PDIAG_n 34 PDIAG_n
35 DA0 35 DA0
36 DA2 36 DA2
37 CS0_n 37 CS0_n
38 CS1_n 38 CS1_n
39 DASP_n 39 DASP_n
40 GND 40 GND

8002
140mm

8003
140mm

8008
tbc mm

8001
120mm

8010
280mm

8007
180m

8012
140mm

8013
tbc mm

to be confirmed if
8011 and 8012
needs to be

to be confirmed if
8008 and 8013
needs to be
combined

8014
220mm

For DVDR 3365 only

For DVDR 3365 only

Not for DVDR 3305

EN 22

3139 785 3093x

6.Block Diagrams, Waveforms, Wiring Diagram.

Waveforms

Waveforms of Analog Board

F204 BOUT F206 GOUT F207 ROUT F209 YCVBS_OUT1 F417 VDrain (No Disc) F417 Vdrain(Standby) F602 CVBS

F604 Y_OUT

F605 C_OUT I303 AFER I304 AFEL I310 ARADC I311 ALADC

I315 AOUT1L I317 AOUT1R I407 Vgate (No Disc) I407 Vgate (Standby) I409 VSource (No Disc) I409 VSource (Standby)

I906 Tstpoint

7500MSP XTAL IN 7500MSP XTAL OUT

I110 SIFOUT

I719 ALDAC

I721 ARDAC

EN 23

3139 785 3093x

6.

Block Diagrams, Waveforms, Wiring Diagram.

Waveforms of Digital Board

IC 7211 PIN 45 IC 7211 PIN 46 IC 7401 PIN74 IC 7401 PIN75 T121

T122 T351 IC7301 PIN 42 T352 IC 7301 PIN 43

T525, T526,T529
CVBS_TU, CVBS_RE,CVBS_FR

T527,T531,T535 SY_RE,SY_FR, CY

T528,T530 SC_RE, SC_FR T532 BPr T533 BPb T537 BCK T538 WCK

T539 DA T540 MCK

EN 24

3139 785 3093x

6.Block Diagrams, Waveforms, Wiring Diagram.

Test Points Overview for Analog Board

Analog Board TestPoint.pdf 2005-07-15

EN 25

3139 785 3093x

Test Points Overview for Digital Board

6.

Block Diagrams, Waveforms, Wiring Diagram.

Digital Board TestPoint.pdf 2005-07-15

EN 26

3139 785 3093x

7. Circuit Diagrams and PWB Layouts

7.Circuit Diagrams and PWB Layouts

Analog: Frontend Video (FV)

I103 G5
I104 G5
I105 G6
I106 G6
I107 E2
I108 F2
I109 G2
I110 F3
I111 E5
c710 G1

A

B

C

D

E

F

G

H

from CU

to MSP

5104 G5
5105 G5
7100 C5
I100 C5
I101 C4
I102 F5

456

A

B

C

D

E

d
e
s
u
t
o
n

Bead

not used

from PS

de
s

u
t
on

Bead

F

G

H

23

from/to CU

Bead

Frontend Video FV

123456

1

3101 C4
3102 B5
3103 D4
3104 D3
5100 B2
5101 E6
5102 F3
5103 G4

to IOV

V05

d
esu to

n

da
e

B

0803 H2
1100 G1
2100 C2
2101 C3
2102 B6
2103 D4
2104 E5
2105 E6
2106 F5
2107 G3
2108 G3
2109 H5
2110 H5
2145 F5
3100 C4

2
0
1
5

0803

5VSTBY 5V

5V_FV

BARCODE

I110

u22

5412

5V

33VSTBY

V
5
2

5V_FV

0012

V3.6u74

I109

I108

BC857BW

7100

n0
0

1

7012

5V_FV

n2
2

3012

I103

4
0
1
2

V057u4

5V_FV

2012

n001

5103

n01

5012

c710

GND_TU

0
1
1
2

p
7
4

p
7
4

9012

K74

30
1

3

I100

I101

5V

1
015

u
01

101

2

n
0
1

6012

n
0
1

I106

5104

8
0
1
2

R001

33VSTBY

0u1

10

SDA

SIFOUT

7

VIDOUT

17

VTU

14

101

3

3TM

4T
M

1
2

NC1

2

NC2

3

NC3

4

NC4

5

13

NC5

11

RFAGC

9

SCL

16

AFT

6

AOUT

BB

1

GND1

8

GND2

15

MB

12

81

1TM

2TM

910

2

2Z
QM
T

0
0
11

RENUT

0K1

u22

0015

2013

I104

33VSTBY

I107

5VSTBY

100R

3100

K7
4

4013

Y
B
T
S
V5

I105

I111

I102

5105

SCL_5V

SDA_5V

SIF1

CVBS_TV

3139 243 31893 2005-04-13

EN 27

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Analog: Video In / Out (IOV)

B
D
N
G

Y|CVBSIN-AUX

Y|CVBSIN-TV

CIN-TV

1
D
N
G

DIGOUT

FBIN-AUX

B|PBIN-AUX

G|YIN-AUX

R|PR|CIN-AUX

Y|CVBSOUT-AUX

COUT-AUX

Y|CVBSOUT-REC

DECV

YIN-ENC

CIN-ENC

CVBSIN-ENC

B|PBIN-ENC

G|YIN-ENC

R|PR|CIN-ENC

3BCCV

2BCCV

1BCCV

CER-BCCV

CCV

D
DV

SCL

SDA

Y|CVBSIN-TUN

6

5

4

3

2

1

D
D
N
G

CIN-TUN

C-GATE

Y|CVBSOUT-TV

FBOUT-TV

B|PBOUT-TV

G|YOUT-TV

R|PR|COUT-TV

CER-BDNG

2D
N

G

1%

1%

1%

1%

DNG

TUOG

DNG

2E

*

to CINCH

1%

1%

R1TUOA

to CINCH

%1

DNG

%1

I211 G7
I212 G7
I213 G7
I214 F7
I215 F7
I216 E7
I217 E7
I218 E7
I219 E7
I220 E7
I222 G13
I223 F13
I224 G13
I225 G14
c200 H14

1%

L2TUOA

F234 H11
F235 H11
F236 H11
F237 H10
F238 H10
F239 H10
F240 I12
F250 I2
F251 I2
F252 I2
F253 I2
I200 D8
I201 D9
I202 E9
I203 E9
I204 E9
I205 F9
I206 G9
I207 H7
I208 G7
I209 G7
I210 G7

1%

to CINCH

SCART FS (Pin 8) In/Out loop through

DNG

#

R2TUOA

AOI morf

L
1
NIA

F222 A10
F223 A9
F224 H12
F225 H12
F226 H12
F227 H12
F228 H12
F229 H11
F230 H11
F231 H11
F232 H11
F233 H11

PSM,AOI ot

1TUOSBVCY

DN
G

DNG

F204 A6
F205 A6
F206 A5
F207 A5
F208 A5
F209 A4
F210 A4
F211 A4
F212 A12
F213 A12
F214 A12
F215 A12
F216 A11
F217 A11
F218 A11
F219 A10
F220 A10
F221 A10

DNG

2NI

S
BVC

Y

to CU

%1

PSM,AOI

o
t

to CINCH

7208 D14
7210 E8
7212 F14
7213 G13
7217 H5
7219 I5
9160 H10
9161 H10
9168 H10
9239 H3
9241 I3
F200 A7
F201 A7
F202 A7
F203 A6

DN
G

1
NISB

V
C

desu t

o
n

DNG

%1

6204 B5
6205 B6
6206 B9
6207 B10
6208 B11
6209 B11
6210 B12
6211 B13

6215 B7
6217 B8
6218 B6
6219 C10
6220 C12
6221 C11
7202 C3
7203 C14
7205 D3
7206 D4

to CINCH

DNG

)CN( 05P

3259 G14
3260 G13
3261 G9
3262 G10
3267 H5
3268 H5
3269 H10
3270 H5
3271 I4
3272 G12
3273 G12
3274 H12
3275 H12
3276 H12
3277 H12
4240 I3
5200 D8
5201 D9
6200 B4
6201 B4
6202 B5
6203 B5

L2NIA

L1TUOA

DNG

DNG

NIB

DNG

3238 D4
3239 D13
3240 D4
3242 D3
3243 D13
3245 D13
3246 E7
3247 F7
3250 F13
3251 F13
3252 H4
3253 F4
3254 G7
3257 F13
3258 G13

CN

FROM FV

1E

#

*

%1

3216 B5
3217 B5
3218 B4
3219 B5
3221 C10
3222 C4
3224 C12
3225 C11
3226 C13
3227 C3
3228 C11
3229 C3
3230 C13
3233 C13
3234 D3
3235 D10
3236 D10

TUOB

to CINCH

PSM morf

N
IC

R

AOI morf

Video Aspect ratio Detection

3200 A13
3201 A14
3202 A8
3203 A8
3206 B4
3207 B9
3208 B11
3209 B11
3210 B12
3211 B13
3213 B7
3214 B8
3215 B4

1%

Video In/Out IOV

1%

)C
N(
05P

NIG

AOI ot

U
C
o
t/
m
or
f

AOI ot

2235 G9
2236 G14
2237 G9
2239 I3
2240 I3
2241 I3

PSM morf

DNG

2TUOSBVC

R2NIA

from/to DIGTAL BOARD

2212 D8
2213 D8
2214 D7
2215 E9
2216 E9
2217 E9
2218 E9
2219 E9
2221 E9
2222 E9
2224 F7
2225 F9
2226 F6
2227 F9
2228 F7
2229 F14
2230 F11
2232 G13
2233 G9
2234 G9

DNG

TUOBF

2201 B3
2202 B12
2203 B12
2207 B7
2209 B8
2211 D8

R1NIA

10 11 12 13 14

A

*

*

*

TUOR

FROM CU

from PS

*

11 12 13 14

123456789

DNG

NIBF

from CINCH

CN

%
1

%1

12345678910

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

I

1201-1 A8
1201-2 A14
1201-3 A9
1204 I12
1205 I1
1206 I10

3261

I217

100n

150R

2213

3277

150R

21C-483XZB

0126

R57

I201

6123

5VSTBY

0
0
2F

3254

10K

5VSTBY

5V

R57

9023

R051

F253

B9

5223

B91

B2

B02

B1
2

B3B4B5B6B7

B8

B1

B01

B11

B21

B31

B41

B51

B61

B71

B
8
1

2-1021

B_WOR

2022

p074

5NSTBY

1226

21C-483XZB

21C-483XZB

8126

9241

K001

3123

5122

n
0
01

5VSTBY

2
5
23

K0
1

2218

1u0

2234

1u0

5

6

789

91

2

02

1
2

2
23242

3

41011121

314151

6
1

718

1

4021

A-KRTB-NMF42

1
12F

1523

0K1

I214

9161

R051

0623

3259

150R

I219

2226

1u0

5126

21C-483XZB

K01

3523

I203

5NESD

2
02F

932

F

5V

33

100n

2232

02

42

03

23

6
3

7

19

1

41

25

21

9
3

15

1029

17

931

37

38

8

44

2

14

16

18

35

34

3

21

62

2
2

13

1127

28

6

43

40

23

4

5

42

MATRIX

VIDEO SWITCH

Φ

STV6618

7210

6026

2
1C-

4
8
3
X
ZB

I207

I210

150R

3272

212F

I208

4240

5V

5NESD

9239

I220

5026

7K4

9323

2
1
C-4

8
3XZB

100K

3268

5V

I218

150K

3240

BC847BW

7205

470p

522I

2228

5VSTBY

F250

I213

21C

­483XZB

8026

21C-483XZB

I205

5NESD

9026

9168

7123

R
5
7

5NESD

5NESD

00
2

6

R0
0

1

21
C

­4
8
3
X
ZB

1023

R001

3023

2225

1u0

8V6C-483XZB

2026

21C-483XZB

1126

1u0

2237

SCL_5V

8V6C-48

3
XZ

B

3026

I212

I216

5V

3
2
2F

922F

5NESD

822F

5323

R57

56K

3243

722F

820R

3222

3K3

6223

R5
7

GND_V

GND_V

6
023

712F

8
323

K001

2230

1u0

1122

n001

21C-483XZB

9160

522F

0226

I224

I211

I222

0523

K72K22

8523

602F

622F

122F

1201-3

MT1MT2

MT2

035 0 8081 90

2235

I215

1u0

9022

p074

0025

u
01

5NSTBY

5NESD

832F

2241

2222

1u0

16V 10u

R57

8023

BC847BW

7208

7202
BC847BW

5NESD

I200

R001

0023

222F

3257

100R

6323

R051

7
0
2F

F251

4123

K001

1026

8V6C-

4
83

XZ
B

2122

u74

2217

1u0

V3.6

A8

A9

R093

9223

A81

A
9
1

A2

A02

A12

A
3

A4A5A6

A7

A1

A
0
1

A
1
1

A
21

A31

A41

A
51

A61

A71

1

­1
0
21

A_WOR

09
1808

0
5
30

7203
BC847BW

612F

3273

150R

5V

c200

3247

150R

K
0
01

7623

12VSTBY

2221

1u0

302F

7026

8V
6
C­4

8
3
XZ

B

012F

4026

8V
6
C-48

3
XZ

B

032F

2233

1u0

1u0

2219

I206

K001

1123

R57

022

F

1223

I209

K001

0123

9K3

3245

132F

96
23

R
05

1

5NESD

402F

GND_D

u74

1u0

2224

V3.6

6122

R
5
7

912

3

K0
1

07
23

9
1
2
6

8V6C-483XZB

22K

F240

3230

5NESD 5NESD

n001

332F

43
2
F

9222

232F

102F

R051

5123

8
0
2F

150R

3274

5VSTBY

3276

3275

150R

12VSTBY

150R

7213

422F

5NESD

BC847BW

K33

2423

812F

BC857BW

7217

412F

7023

512F

678

9

R57

5
2

62

72

82

9
2

3

0
3

4

5

516171

81

91

2

02

12

22

32

42

6
02

1

A-KRTB-NMF03

1

01

1
1

21

31

41

322I

K
9
3

3234

1
022

p0
0

1

BC847BW

312F

GND_D

7219

2227

47n

9K3

3323

3022

p074

5VSTBY 5V

632F

53
2F

75R

3246

22K

3271

7206

BC847BW

150R

5VSTBY

F252

I204

3262

4122

5VSTBY

12VSTBY

n001

10
2

5

u01

912F

6322

n001

73
2F

7126

21C-483XZB

7212
BC857BW

2023

SDA_5V

R001

3227

27K

902F

4223

R57

1
2
3
4
5
6
7
8
9

I202

B9B-PH-K

1205

70
2

2

p074

2239

10u16V

1u0

2240

8123

R
57

8223

R051

DGO2

502F

5NESD

D_UB

Y_FIN

YFIN

C_FIN

CFIN

CVBSFIN

CVBS_FIN

GND

AINFR AINFR

AINFL AINFL

D_CVBS

SBVC_D

Y_D

D_Y

RV_D

D_VR

GY_D

D_YG

BU_D

B
U_A

RV_A

N

IF
_Y

NIF_Y

NIF_SBV

C

RAER_C

RAER_SBVC

GND

GND

GND

D_DNG

D_DNG

D_DNG

V_DNG

V_DNG

V_DNG

V
_DNG

V_DNG

V_DNG

V
_D

N
G

V_DNG

NI
F
_SBVC

N

IF_

C

N

IF_

C

G
Y_A

C_D

CVBS_TV

VT_SBVC

VT_SBVC

RAER_Y

D_DNG

D_DNG

D_DNG

L1NIA

R
1NIA

1CS8

NI
BF

I_SF_2S

S2_FS_I

L2NIA

R2NIA

R2TUOA

L2TUOA

R1TUOA

DGO2

8SC1S2_FS_I

CRout

L1T

U
O
A

8SC2_1

8SC2_2

DGO4

3139 243 31893 2005-04-13

EN 28

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Analog: Audio In / Out (IOA)

G4

0

3

2

VDD

VEE VSS

1

0

3

2

1

4X

030

1

G4

0

3

2

VDD

VEE VSS

1

0

3

2

1

4X

030

1

I307 C5
I308 D5
I309 C2
I310 B9
I311 C9
I312 D6
I313 D6
I314 D8

I315 D9
I316 E6
I317 E9
I318 C2
I320 B2

*

from IOV

Options

3320 E8
3321 E9
3322 E4
3323 E4
3324 F4
3325 F4
7300-1 B7
7300-2 B7
7301-1 E7
7301-2 D7
7302 A5
7303 C5
7304 D9
7305 E9
7306 E3
7307 E4
7308 F3
7309 F4
I300 B2
I301 B2
I302 C2
I303 D2
I304 D2
I305 A4
I306 B4

3310 B6
3311 C6
3312 D6
3313 D7
3314 D8
3315 D8
3316 D9
3317 E6
3318 E7
3319 E8

*

from DAC_ADC

*

*

*

false type

from CU

*

2318 E7
2319 E8
2320 A8
2321 A9
3300 C3
3301 C3
3302 C4
3303 C4
3304 E2
3305 E2
3306 E2
3307 E2
3308 E3
3309 E3

Audio In/Out IOA

false type

2304 C2
2305 C2
2306 D2
2307 D2
2308 D2
2309 D2
2310 B6
2311 A7
2312 B7
2313 C6
2314 C7
2315 D7
2316 D7
2317 D8

from MSP

from DAC_ADC

from MSP

from IOA

6789

A

B

C

D

E

from IOV

from IOV

from IOV

from PS

from DAC_ADC

from MSP

to DAC_ADC

56789

12345

1234

to IOV

from IOV

F

A

B

C

D

E

F

2300 B1
2301 B1
2302 C2
2303 C2

from IOV

5NSTBY

to DAC_ADC

to IOV

from CU

2300

1u0

4033

K001

8
1
32

p001

0132

0n1

I308

123

2

V

3.
6

u7
4

I303

1033

K001

5NSTBY

V3.6u74
02
32

613
I

5VSTBY

I304

323

3

K01

2301

1u0 2302

1u0

5VSTBY

5VSTBY

31
3I

1u0

2307

I315

1u0

2304

2312

100n

2309

1u0

2

1

84

5VSTBY

MC33078D

7300-1

3

7301-1
MC33078D

3

2

1

8

4

I305

R
02

8

9
13

3

I318

5

6

7

84

7300-2
MC33078D

1u0

2303

7305
BC817-25W

I306

BC817-25W

7304

K
0
01

20
3

3

K00

1

5033

5NSTBY

I317

2317

10u 16V

3313

220R

K
00

1

I320

3033

2305

1u0

5NSTBY

5NSTBY

5VSTBY

2319

I310

5VSTBY

10u 16V

1u0

2308

1

14

5

15

2

11

4

13

3

10
9

6

61

7

8

12

MDX

HEF4052B

7302

3311

1K0

6132

0n1

5V

K01

42
33

I307

6033

K0
01

I301

5NSTBY

2314

100n

5VSTBY

2311

100n

100n

2315

5NSTBY

I302

41
33

R028

3132

p001

1u0

2306

3321

8033

K001

5

6

7

84

4K7

7301-2
MC33078D

K001

7
033

0033

I312

K001

K
00

1

9
033

5VSTBY

BC847BW

7307

K01

5233

7309
BC847BW

BC847BW

7308

I311

5NSTBY

3312

1K0

5VSTBY

5VSTBY

1K0

3317

3310

1K0

K001

I309

5
133

1

14

5

15

2

11

4

13

3

MDX

10
9

6

61

7

8

12

I300

7303

HEF4052B

3316

4K7

K001

023

3

220R

3318

2
2
33

K01

5V

I314

AIN_SEL1

7306
BC847BW

RSA1

RSA2

AIN_SEL0

AIN2L

AIN1L

AIN1R

AINFL

AINFR

AOUT1L

AOUT1R

AIN2R

AKILL

ARDAC

ALDAC

AFEL

AFER

ALADC

ARADC

3139 243 31893 2005-04-13

EN 29

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Analog: Power Supply (PS)

LRTC

M
E
D

ESNESI

DNG

NIARD

SVH

REV

I
RD

CCV

3

12

15

1

13

17
18

14
16

11

10

5

NC

4

8

6

7

2

LOW = STANDBY

GND

GND

GND

V
5

I440 G13
I441 H10
I442 H11
I443 I10
I444 H12
I445 H12
I446 D13
c300 D9

V003

F452 I9
F453 H11
F455 H12
F456 H13
F459 H14
I400 B3
I401 B4
I402 B5
I403 B5
I404 C4
I405 C6
I407 D4
I410 E6
I412 F6
I420 I7
I423 H8
I424 H8
I426 B7
I427 A10
I428 A11
I429 A12
I430 B12
I434 F8
I435 F10

F417 F6
F418 I6
F419 B6
F421 A8
F422 A9
F424 A13
F425 A13
F427 A14
F428 C8
F430 B12
F431 B12
F433 C13
F435 D8
F436 E9
F437 D9
F439 D10
F441 E8
F443 F13
F444 F8
F445 F8
F447 F9
F449 G9
F451 F14

V9,31

draoB latigiD ot

V2

7419 F13
7420 H8
7421 H9
7422 H11
7423 H12
9400 E1
9401 A13
9402 H13
9403 B13
F400 B1
F401 B2
F402 B3
F403 C1
F404 C2
F405 B3
F406 E1
F407 E1
F408 E2
F409 G1
F410 E2
F411 F2
F412 E1

F413 E4
F414 F4
F415 G1
F416 G1

HI = ON

6417 F11
6418 G11
6419 G13
6420 H10
6421 I10
6422 I12
7400 G3
7401 D4
7402 E2
7403 H6
7404 I6
7405 A10
7406 B10
7407 B11
7408 A12
7409 A12
7410 A13
7411 B10
7412-1 C10
7412-2 C11
7413 C11
7414-1 D11
7414-2 D11
7415 D13
7416 E12
7417-1 E11
7417-2 E12
7418 F11

4401 D13
5400 D7
5401 C4
5402 D6
5403 A9
5404 C9
5405 D9
5406 F9
5407 G9
6400 B4
6401 B5
6402 C5
6403 C4
6404 D5
6405 E5
6406 G4
6407 H5
6408 A8
6409 C8
6410 C8
6411 D8
6412 E8
6413 F8
6414 F8
6415 G8
6416 G11

1V

3457 D12
3458 D11
3459 D12
3460 D13
3461 E11
3462 E11
3463 E11
3464 E12
3465 E13
3466 E13
3467 E13
3468 E12
3469 E13
3470 F10
3471 F11
3472 F12
3473 F12
3474 F13
3475 G12
3476 G13
3477 H9
3478 H11
3479 H12
3480 H11
3481 H12
3482 B8

Power Supply PS

3483 B8
3484 B8
3485 B8
4400 H2

3426 H7
3427 G8
3428 H8
3429 A10
3430 B10
3431 A10
3432 A11
3434 A12
3435 A12
3436 A11
3437 A11
3438 B9
3439 C9
3440 C10
3441 C11
3442 C11
3443 C11
3444 C11
3445 C11
3446 C12

3447 B13
3448 B13
3449 B13
3450 B13
3451 D10
3452 D10
3453 D10
3454 D12
3455 D12
3456 D12

2434 G13
2435 H9
2436 I12
2437 B10
3400 A6
3401 A6
3402 C3
3403 B4
3404 C5
3405 C5
3406 C6
3407 F2
3408 E3
3409 E4
3410 E5
3411 F4
3412 F5
3413 F5
3414 F6
3415 G4
3416 G4
3417 I4
3418 H6
3419 H6
3420 H7
3421 H7

GND

3422 I7
3423 I7
3424 G8
3425 H8

2403 C6
2404 C5
2405 C6
2406 E4
2407 D5
2408 E4
2409 G6
2410 H4
2411 H5
2412 I5
2413 H7
2414 I8
2415 B7
2416 A9
2417 A10
2418 C9
2419 C11
2420 D9
2421 D9
2422 D9
2423 D12
2424 E9
2425 E10
2426 E11
2427 E12
2428 F8
2429 F9
2430 F10
2431 G9
2432 G11
2433 G12

U67 H6
U68 I6
U69 I7
U70 G8
U71 H8
U74 A6
U78 A13
U79 C9
U80 D9
U82 F12
U83 G12
U84 F12
U85 F13
1400 C1
1401 D1
1402 G1
1403 B2
1404 B2
1405 B3
1406 A13
1407 B12
1408 C10
1409 D10
1410 F9
1411 H13
2400 C3
2401 D2
2402 B4

GND

eni
g

nE cisaB o

t

1234567891011121314

12345

GND

U64 G5
U65 H5
U66 I3

11 12 13 14

A

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

I

U60 E5
U61 F3
U62 F5
U63 G4

2
3
4
5
6
7
8
9

678910

1401

B12P-PH-K

1

10
11
12

2415

2n2

3466

120R

I428

GND

U63

F411

GND

F403

GNDHOT

7402

SI2306DS

n00

1

0342

470R

3455

2000mAT

1408

5NSTBY

GND

3Vreg

1
0
44

5VSTBY

F408

5Vreg

5V

GND

1543

9K3

324

3

K6
5

3439

2K2

U68

F430

2

6

1

BC846U

7412-1

12V

3456

470R

F428

F416

F435

91
4
7

2
24F

B

9443

0K1

3460

10K

K001

9243

7443

0K1

5243

2
K2

3426

4K7

GND

F451

8
2
43

R01

7420

BC847BW

GNDHOT

12VSTBY

I400

2045

I401

GNDHOT

12VE

YB
T

SV8

3419

470R

STP16NF06FP

7413

0n1

5N

12V

6042

1u0

46U

7418
BC337-25

2408

GND

1
2

204I

1400

B2P3-VH

u
22

2
34
2

3476

10K

GND

164

3

9K3

3434

K74

SB340

6410

76U

40
47

2

A

1

K

3

R

9403

ZCA134LT

7410

PDTC124EU

n00

1

I440

4
34
2

5
242

u065

I445

6402

1N4006

2402

1n0

F421

K
0
1

0743

5Vreg

7342

V
05

2
u
2

18K

5406

22u

3464

GND

GND

K022

0343

3342

n01

F401

9242

u
001

12VE

F425

5N

I427

STS9NF30L

7416

7421

BC847BW

2403

1n0

I435

0142

n
0
01

3462

2K2

3454

3K9

F404

I426

GND

33VSTBY

3465

220R

GNDreg

3453

100R

SI2306DS

7415

8043

R001

1405

F424

DNG

I405

100V

T125mA

1410

4
243

2
K2

2743

0K1

0242

0m1

F410

3415

1M0

GND

5403

22u

8242

0m1

T

6403

1N4006

1407

1000mA

3400

F453

3M3

3452

12VSTBY

2K2

F406

9400

12VSTBY

5V_FE

5V_BE

6416

1N4935

K
22

GND

BC846U

2

6

1

7243

7414-1

F400

SI2306DS

7405

GNDHOT

3407

10K

I404

1402

B4B-EH-A

1
2
3
4

VGNSTBY

BC847BW

7406

6417

3467

2K7

GND

BZX384-C6V8

GND

GND

GND

3457

2K2

I444

GND

1404

GND

12V

5ET

1342

2
n2

U79

5VSTBY

GND

7
K2

GND

95
43

2n2

2409

F443

g
erV5

GND

3441

3K9

GNDHOT

F436

I420

U65

7417-2

BC846U

5

3

4

2

6

1

BC846U

7417-1

414

2

n001

M2
4

TYB

4046

F427

GND

12VE

6043

K
0
33

2
0
4
3

I407

K086

GND

470R

3443

YBTSV33

GND

6
4
4
3

7
K2

2413

100n

6
34
2

n001

3473

1K0

3V3SW

11
4
2

V05u2

2

414

3

R028

470R

3442

I430

F441

1

6

2

7

5

1

7411
STP16NF06FP

0047

LO
R

T
NOC SPM

S

Φ

P7051AET

3

4

8

244I

12VE

71
4
3

7
K4

220R

R001

3403

GND

8743

K022

634

3

V
0
04

u86

40
4

2

0
K
1

0
5
43

1K0

3418

9
6
43

5
K
1

5VE

12VSTBY

F402

12V

9402

PDTC124EU

7407

GND

F412

6409

SB340

22u

5404

n022

0042

F444

12V

GND

U61

L

I
AF

_
REWOP

3411

3K3

0
246

2V
8
B-9
7
XZ
B

I412

1246

61
3
S
A
B

6412

STPS5L40

U62

3V3SW

12VE

U74

W
B

758CB
3
24
7

F414

33VSTBY

2u2

5405

F431

F422

F409

F407

5146

6
V5

C

-48

3
XZB

2246

10R

72C

­483

XZ
B

STPS5L40

6411

3420

EB_V5

3143

R028

U80

8343

0m1

6
1
42

9K3

500mA T

1406

5

3

4

3421

5K6

BC846U

7414-2

I429

GND

GND

I441

GND

U82

GND

1042

6
13

S
AB

GND

p074

c300

4
146

GNDreg

F445

1403

6418

1N4935

PTF/65

50
4
3

U83

K033

GND1

K033

40
4
3

7422
BC547B

100R

3463

3445

1K0

4400

2427

1n0

84
4
3

0
K1

U60

GNDHOT

F439

K74

2343

F415

F456

GND

125mAT

3475

10K

GND

1411

1
2
42

u065

560K

3416

5407

6406

BAT54 COL

GNDHOT

17U

4
34
I

9146

33B-97XZB

3474

GNDHOT

344
I

1K0

6400

1N4006

6401

1N4006

15

16

17
18

2

3

5

7

9

SRW28EC9

5400

10

11

12
13

14

SI2306DS

7408

GND

3401

3M3

GND

U69

GND

7042

p7
4

F437

WS3V3

7401

GND

STP3NK60ZFP

U78

2
54F

2426

1n0

STPS3L60-C2

D
N
G

3K3

6408

5042

5343

I410

n74

07U

GNDreg

86R0

0143

GND

GNDHOT

5Vreg

I423

GND

GND

1n0

2419

GND

GND

GND

9401

7743

7K4

2243

7K
4

U85

GNDHOT

1n0

2422

1K0

3458

7409

BC847BW

2418

1n0

F405

U84

GNDreg

R0
28

GNDHOT

214

3

F419

3K3

1343

7
04
6

1
2
VA

B

F449

314F

F418

47R

K001

3479

7343

100R

3440

F433

5401

HF2022R

12

43

I403

2K2

3444

F459

u033

7142

0m1

4242

1K5

32

TOHD

N
G

GND

3471

TCET1108

14

0K1

5843

7403

0K1

4843

3843

0K1

GND

0K1

2843

SBYV27-200

6413

3

4

F455

GND

7412-2

BC846U

5

5342

I446

n
001

2K2

F417

3480

I424

1409

T4A

U66

2423

1n0

5046

7
4
R0

3004N1

3481

9043

EV5

GNDHOT

2K2

2142

n00

1

1K0

F447

3468

3V3SW

12V

5V_FE

DD_ON

STBY

5V_BE

12VEF

5N

5VEF

3V3SW
3V3SW

12VE

5VE

3139 243 31893 2005-04-13

EN 30

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Analog: Multi Sound Processing (MSP)

LOUDSPEAKER L

D/A

D/A

I2SL/R

HEADPHONE R

IDENT

NC

SCART

LOUDSPEAKER R

A/D

D/A

DEMODULATOR

S1...4

FM1
FM2

I2SL/R

NICAM B

NICAM A

SCART-L

HEADPHONE L

IDENT

LOUDSPEAKER

A/D

D/A

SCART-L

SCART-R

DFP

SCART-R

Switching Facilities

I521 D7

I522 D7
I523 E7
I524 D8

from/to CU

from DAC_ADC

I525 E8
I526 D8
I527 F8
I528 E9
I529 F9

7500 A3
7501 A9
7502 E9
7503 F9

to IOV

to IOA

7504 A8
I500 B2
I501 B2
I502 C2
I503 C2
I504 D2
I505 D2
I506 D2
I507 D2
I508 E1
I509 E2
I510 E1
I511 E2
I512 A4
I513 A4
I514 A6
I515 A6
I516 A6
I517 B7
I518 B7
I519 B7

B

C

D

E

from PS

to IOV

from FV

Multi Sound Processor MSP

2524 E7
2525 E8
2526 F8
3501 B2
3502 B1
3503 D2
3504 D2
3505 E1
3506 E1
3507 E1
3508 E1
3509 A4
3510 A4
3511 A7
3512 A7
3513 B8
3514 D8
3515 E8
3516 E9
3517 E9
3518 A8
5500 F5
5501 B8
6500 B7

2520 D7
2521 E7
2522 E7
2523 D7

to IOA

from CU

123456789

123456789

A

B

C

D

E

F

A

from DAC_ADC

from DAC_ADC

from IOV

from/to CU

from IOV

F

1500 F6
2500 A2
2501 C2
2502 C2
2503 D1
2504 D1
2505 E2
2506 E2
2507 F5
2508 F6
2509 F7
2510 A6
2511 A6
2512 A6
2513 A7
2514 A7
2515 C8
2516 B8
2517 C7
2518 C7
2519 D7

2152

V
52u01

I524

I503

K01

8153

BC847B

7504

25V10u

2523

I525

2
1
5
3

K22

2252

0n1

51
5

I

7152

0n1

3152

n001

V
0
5

7
u4

9152

1u0

2505

I501

00
5

2

V
52u

01

2
1
5I

3
15
I

PDTC124EU

7501

P
T

92

1FERV

52

2F
E

RV

24

PO
T

FER

V

5

NI_LAT

X

6

TUO_LATX

I504

41 SC1_IN_R

31SC1_OUT_L

30SC1_OUT_R

37 SC2_IN_L

38 SC2_IN_R

11

STBYQ

4

NETSET

7

I2S_DA_OUT

15

I2S_WS

43 MONO_IN

324282

23

22

RESETQ

40 SC1_IN_L

DVSUP

9

0OI_RTC_D

8

1
OI
_
RTC_

D

12

I2C_CL

13

I2C_DA

14

I2S_CL

17

I2S_DA_IN1

21

I2S_DA_IN2

16

9
3

GSA

44

SSVA

1

PU
S

VA

4
3

M_LPAC

27DACM_L

26DACM_R

02

S
S
VD

19

81

LC_RDA

01

LES_RDA

36

AGNDC

53

SS
V

HA

3
3

PUSVHA

2 ANA_IN+

3 ANA_IN-

7500
MSP3415G

52
52

0n
1

705

2

n
001

I510

I518

415I

I528

0
n1

8152

I519

0n1

6
252

7503

BC817-25W

9
052

3p3

K21

7
053

8
053

K21

2504

2u2 50V

56p

2502

u01

5152

I509I508

2506

1u0

2K2

3505

5V

25V10u

2524

I517

BC817-25W

7502

6
1
3SAB

005

6

8VSTBY

8VSTBY

I500

50V2u2

2503

3503

1K0

I506

5V

3p3

8
052

K
0
1

90
5

3

2501

56p

5VSTBY

1500

18M432

I521

3511

12K

I526

220R

3514

11
5

2

n
01

025

2

n01

I511

I502

7
K
4

715

3

V
52u01

0152

3501

100R

3
15

3

7K4

5V

01
53

K01

3506

2K2

GND_TU

8VSTBY

V61u7

4

4152

I529

I527

3515

220R

105

5

u01

I505

6153

7
K
4

5V

0n1

12
52

1K0

3504

5500

10u

100R

3502

5V

I507

I523

615I

n00

1

615

2

STBY

I522

AKILL

AIN1R

AIN1L

ARDAC

ALDAC

AOUT2L

AOUT2R

1
A
SR

2AS

R

SCL_5V

SDA_5V

SIF1

AFEL

AFER

3139 243 31893 2005-04-13

EN 31

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Analog: Audio Converter (DAC_ADC)

DATAO

BCK

WS

VSSA VSSD

VDDD

VINR

SFOR

VINL

MSSEL

VREF

VRN

VDDA VRP

SYSCLK

PWON

SDA
CDIN

CCLK

SCL

AD0

CS

VQ

VBIAS

GND

SDIN

AMUTEC
BMUTEC

AOUTA
AOUTB

DEM

SCLK
LRCK
MCLK
RST
DIF0

DIF1

VLVDVA_HVA

I704 E1
I705 D4
I706 D3
I707 D3
I708 D3
I709 E5
I710 D6
I711 E5
I712 F5
I713 F5
I715 B8
I716 C8
I717 C8
I718 D8
I719 D9

Audio Converter DAC_ADC

to cinch

I720 D8
I721 D9
I722 C5
I723 A6
I724 F5
c700 F9

7702 C2
7703 B6
7704 D6
7705 B8

7706 C8
9014 F5
F700 C1
F701 C1
F702 C1
F703 D1
F704 D1
F705 D1
F706 D1
F707 D1
F708 D1

GND

to DIGIO

F709 D1
F710 D1
F711 E1
F712 E1
F713 A8
I700 A1
I701 A4
I702 B2
I703 E1

3715 E1
3716 A6
3717 C5
3718 C5
3719 C7
3720 B9
3721 B8
3722 C9
3723 C9
3724 D9
3725 D9
3726 D9
3727 E9
3728 D4
3729 F4

from PS

GND

to IOA,MSP

3730 F5
3731 C5
3736 A3
3737 B4
3738 B4
4700 B2
5700 A6
5701 D5
6700 B2
6701 B1
6703 C2
7700 A2
7701 A3

2718 B7
2719 B7
2720 B8
2721 B8
2722 B8
2723 C8
2724 C9
2725 D8
2726 D9
2727 D8
2728 E9
3700 B1
3701 B1
3702 A2
3703 C2

from PS

GND

GND

GND

from IOA

DAINCOAX

from DIGIO

3706 D2
3707 D2
3708 D2
3709 D2
3710 D1
3711 D2
3712 D1
3713 E2
3714 E1

DAOUT

123456789

1

GND

2703 D3
2704 D3
2705 D3
2706 E1
2707 E1
2708 F4
2709 F4
2710 E5
2711 E5
2712 D7
2713 C5
2714 B6
2715 B6
2716 A7
2717 B7

B

C

D

E

F

A

B

C

D

E

F

1700 E1
2700 B1
2701 B3
2702 D3

GND

from DIGIO

GND

GND

draoB latig

iD ot/mo

rf

DAINOPT

from IOA

GND

23456789

A

K001

8373

K22

7
37

3

n
22

1072

PDTA124EU

7701

I705

0n
1

6
272

8273

K74

c700

3724

680R

F709

5NSTBY

A

F713

u01

1075

I712

0
2
73

9K3

12VSTBY

3722

4K7

F704

n001

1272

I704

A

n001

I711

807

2

6.3V47u

2706

GND

I722

A

DNG

I718

F712

A

p
33

407

2

3V3SW

5VSTBY

A

50V 10u

2727

BC847BW

7706

I715

3V3SW

K01

5NSTBY

10u

5700

7
1
73

3731

100K

I716

n22

9172

1
0
73

K2
2

AGND

4700

6373
K
2
2

5VSTBY

I701

5VSTBY

GND

5NSTBY

DNG

5NSTBY

I713

I708

6701

BAS316

K72

727

3

DN
G

A

I702

9014

F711

12VSTBY

A

4172

V3.6u

0
01

7705
BC807-25W

3707

22R

7702
PDTC124EU

D
NG

V3
.6

01
72

u001

GND

3712

22R

I706

BAS316

6700

A

GND

2725

10u50V

I717

8272

0
n1

F702

10K

3714

I709

5273

K72

680R

3726

V
3
.6

F710

5V

9072

u74

3V3SW

5VSTBY

7700

PDTA124EU

V057u4

8172

p33

3072

2
1
72

n
001

5VSTBY

GND

22R

3713

4
10

2

1

11

7
1

12

502

13
19

18
15

14

9

8

7

6

61

3

0
1

12

7703

CS4351

192 kHz DAC

Φ

6

8

61

9

1

3

2

4

5

51

7704
UDA1361TS

ADC

Φ

24-BIT AUDIO

11

13

14

7

DNG

GND

p3
3

207

2

3V3SW

n001

1172

I721

3V3SW

5VSTBY

22R

3709

DNG

I710

F706

I720

2716

100n

3V3SW

7u4

3172

GND

I724

A

F705

22R

3711

917

3

K01

3706

22R

5V

n22

I719

D
N
G

0
0
72

GND

AA

2723

100n

22R

3708

DNG

1273

0K1

K01

8173

12VSTBY

A

A

0073

K
00

1

I700

0272

V6
1
u74

3710

22R

GND

5VSTBY

2707

47u 6.3V

p3
3

507

2

F707

3073

7K4

5172

n001

47u

2722

GND

K22

2073

16V

n001

4272

K74

9
27

3

GND

DNG

F703

I723

3715

10K

DNG

GND

0
3
73

0
K1

F708

I707

F700

A

F701

WS3

V3

I703

3V3SW

3716

4R7

GND

3V3SW

100n

2717

20

21

22

3

4

5

6

7

8

9

11

12

13

14

15

16

17

18

19

2

22FMN-BTRK-A

1700

1

10

BAS316

6703

K01

32
7

3

A_PCMCLK

D_BCLK

BKILL

POWER_FAIL

D_WCLK

D_DATA0

D_PCMCLK

DKILL

DAINCOAX

DAINOPT

A_BCLK

DAOUT

A_WCLK

MCLK

LRCK

SDIN

SCLK

ALDAC

ARDAC

AMUTEC

BMUTEC

LRCK
MCLK

SCLK

SDIN

AKILL

A_DAT

ALADC

ARADC

3139 243 31893 2005-04-13

EN 32

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Analog: Digital In / Out 1 (DIGIO 1)

1

1

1

1

1

1

F905 E8
F906 F8
F907 F8

to DAC_ADC

I900 A4
I901 B3
I902 D1
I903 D2
I904 E3
I905 D3
I906 D4
I907 E4
I908 D6

A

B

C

to DAC_ADC

SP morf

OUT

OUT

OPTICAL

Digital In/Out DIGIO1

from DAC_ADC

3907 E1
3908 D3
3909 E3
3910 E4
3911 E7
3912 E7
3913 F6
3914 E8
4812 A4
6900 F9
7900-1 D3
7900-2 E4
7900-3 D4
7900-4 F4
7900-5 E4
7900-6 B3
7901 D6
F900 C9
F901 C9
F902 C9
F903 D8
F904 D7

3904 A4
3905 B4
3906 D1

for DIGITAL IN only

DIGITAL

123456789

123456789

A

B

C

D

E

F

for DIGITAL IN only

de
s

u
t

o
n

D

E

F

0007 F2
1900 C9
1901 D9
2900 A4
2901 A4
2902 D2
2903 E4
2904 D5
2905 D7
2906 D8
2907 F8
3900 C2
3901 B3
3902 B4

10K

3902

F907

F905

R
06

5

0093

F906

F901

I903

GND

3

1

IN

2

VS

JFJ1000

6900

I908

5V

I905

5V

R0
74

2184

70
92

V
52n

001

I901

1

2

34

6

6RG

7901

I906

BRACKET

0007

4
09
I

I907

I902

14

12

470R

3908

74HCU04D

7900-6

13

7

1900

1
2
3
4

1K0

3913

310360100162

3911

75R

2904

7

14

10

100n

74HCU04D

7900-5

11

7093

R001

3906

750R

V
01

5V

5V

10
92

0u1

V5

2K2

3909

2902

100n

100n

2906

0n1

309

2

F902

5
092p051

100R

3901

F900

1

3

2

I900

F903

YKC21-3416

1901

74HCU04D

3

7

14

4

7900-2

K0
0

1

4093

0193

R
065

F904

50
9

3

K001

0
092

1

7

41

2

n01

74HCU04D

7900-1

9

7

4
1

8

7900-4

74HCU04D

3912

82R

6

R
74

4193

74HCU04D

7900-3

5

7

14

DAINCOAX

DAINOPT

DAOUT

3139 243 31893 2005-04-13

EN 33

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Layout: Analog-Main Part (Top View)

Analog_Topview_3355_02.pdf 2005-07-15

EN 34

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Layout: Analog-Main Part (Bottom View)

Analog_Bottomview_3355_02.pdf 2005-07-15

EN 35

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Front: Front Panel

FIP

LED

Φ

FIP

CTRL

DRIVER

X

XT

KEY_R

FM

SCK

D

D_HOST

SCK1

POWER_FAIL

IR

VLOAD

1
2
3

IC

1
2
3
4 POWER_CTL

VDD

VSS

24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

0

RDY

RESET

2

1

2

ATN

HOST_RESET

1

7101 B2
7102 A3
7103 B3
7104-1 D1
7104-2 D2
7104-3 C3
7104-4 C4
7104-5 D3
7104-6 D4
7105 E7
7106 I5
7107 H13
F100 B2

I107 A4
I108 A4

F116 E13
F117 E13
F118 E13
F119 E13
F120 E13

F114 H5
F115 E8

6102 D9
6103 D9
6104 D9
6105 D10
6106 D10
6107 D10
6108 D9
6109 E3
6110 F3
6111 F3
6112 H3
6113 G3
6114 G3

F121 F13
F122 F13
F123 F13
F124 F13
F125 F13
F126 F13
F127 F13
F128 F13
F129 H12

6212 H5
7100 C1

3123 B10
3124 B9
3125 B9
3126 B10
3127 B10
3128 I6
3129 G5
3130 D12
3131 D12
3132 E12
3133 H11
3134 H11
3135 F10

I100 B1
I101 B1
I102 B2
I103 A2
I104 A2
I105 B3
I106 B3

6100 A5
6101 D8

2121 G12
2122 G13
2123 F10
2124 F10
2125 I11
2126 F9
2127 G2
3100 B1
3101 B1
3102 A2
3103 A2
3104 A3
3105 A3

F130 E10
F131 E9
F132 F10
F133 F11
F134 F9

3121 A10
3122 A10

1213 F1
1214 F2
1215 F2
1216 F2
1217 F1
2100 B1
2101 B1
2102 B1
2103 B2
2104 A4
2105 A4
2106 A3
2107 B5

WS0

F101 B6
F103 E3
F104 E3
F105 E3
F106 F3
F107 F3
F110 H3
F111 H3
F112 B9

2119 G12
2120 G12

1 2345678910111213

DC0

6115 E3
6116 B1

1211 E2

1 234567

3136 F10
3137 G9
4100 H5

4101 I4
4102 F1
4103 E1
4104 D2
4109 H11
4110 H11
5100 B1
5102 E3

12 13

B

C

D

E

F

G

H

I

A

B

C

D

E

F

3106 C2
3107 A4
3108 A4
3109 B4
3110 B5
3111 B5
3112 B5
3113 D1
3117 G2
3118 G2
3119 H2
3120 H9

1203 A6
1207 F2
1208 E1

2108 B5
2109 D1
2110 G2
2111 G2
2112 H2
2114 I3
2115 I3
2116 I4
2117 H10
2118 G11

8 9 10 11

H

I

0100 E3
1100 E10
1101 F10
1102 H1
1201 F13

G

I106

A

201

4

6109

BAS316

470R

3107

V
5
.
5

GND

41
1

2

m
022

5102

14

8

10R

3122

7104-4

74HCT14D

9

7

1211

EVQ11L05R

5012

V52u01

6112

BAT54 COL

3130

2K7

1014

2112

2n2

10K

3117

GND

F116
F117

1214

6110

BAS316

EVQ11L05R

EVQ11L05R

6115

BAS316

GND

1216

2111

2n2

2

3112

10R

74HCT14D

7104-1

1

7

14

F114

I102

F105

7104-3

74HCT14D

5

7

14

6

2106

22u50V

0K1

3100

6100

BZX384-C6V8

F103

I104

10K3119

3132

2K7

3104

330R

0
K1

6013

2101

220n

6K8

3101

560R

3128

F118

3111

10R

GND

EVQ11L05R

1208

GND

1215

F128

EVQ11L05R

F123

F125

EVQ11L05R

1207

3102

33R

1102

1

GND

u001

BC847BW

7100

GND

5100

BC847BW

7106

K01

80
1

3

9013

R074

3014

GND

I108

F110

2115

V3.60m1

F104

BC327-25
7103

11

7

14

10

7104-5

74HCT14D

n001

0012

3135

100R

F132

I103

4212

p22

p
2
2

3
2
12

1101

32K768

VS

GND

F130

GND

OUT

TSOP4836ZC1

7107

K28

K
28

7
2
13

K28

621

3

5213

4
2
13

K
28

3016

613SAB

F106

4014

13

7

14

12

7104-6

74HCT14D

2n2

2110

n74

801

2

1213

EVQ11L05R

10R

3110

GND

2126

NN
TE
K61

8
L
T
L

I105

3105

470R

R033

3
01

3

F126

I100

F124

F120

F122

F121

F127

F131

F133

F115

GND

K072

0
2
1
3

n01

6113

BZX384-C6V8

7
1
1
2

F107

10R

GND

3123

2K7

3131

2102

220n

9012

0n1

613SAB

5016

3134

100R

GND

100R

3133

F129

GND

GND

GNDGND

GND

F111

BAS316

6111

2103

1n0

7102
BC337-25

3118 10K

7104-2

74HCT14D

3

7

14

4

7

8

9

GND

10

11

12

13

14

2

3

4

5

6

1201

HLW14S-2C7-LF

1

7101
BC847BW

101I

GND

613SAB4016

8016

613SAB

61
3

SAB7016

F101

F119

F112

F134

6212

V
05

2
u2

4109

V61u001

K
746313

GND

8112

I107

613SAB2016

3113

22K

10R

3121

4012

n74

GND

9
21

3

R05

1

F100

0100

WH02D-1

12

2127

2n2

6114

BAS316

6
1
3SAB

1016

13

3137

47K

1100

2

n0
0

1

5
2
12

2P

813P71

4P

61

5P

51

6P417P

318P2

1

9P

01P

11P012

1P

9

31P841P751P

6

5

61P

71P

4

91

22

G8

1

11F

21F

2

13

1
2
F

22F

23

12

CN

0
2

1P

11

92

G1

G
2

82

72

G3

6
2

G4

G
5

52

42

G6

3
2

G7

HUV-08SS65T

1203

613SAB6016

50V

2107

22u

00
1

4

BAS316

n0
1

6
1
1
2

6116

1217

EVQ11L05R

n00

1

021

2

1212

n001

n
0
0
1

2
2
1
2

9112

n
0
01

0
1
14

GND

11

1

27

28

52

51

50

2

3

43
45
46
47
48 44

12

5

4

8

19
20
21
22
23

7

49

13

41

42

34
35

16

36
37
38
39
40

17
18

14
15

24
25
26
29
30
31
32
33

UPD16316GB-006-8ET

7105

6

9

10

POWER_CTL

POWER_FAIL

VGNSTBY

SCK

D_FM

D_HOST

GND

12VSTBY

5VSTBY

KEY_C

KEY_B

KEY_A

RC

POWER_FAIL

D_HOST

D_FM

RDY_FM

ATN_FM

HOST_RESET

SCK

VGNSTBY

5VSTBY

RDY_FM
ATN_FM

HOST_RESET

RC

5VSTBY

5VLP

VGNSTBY

F2

5VSTBY

5VLP

5VLP

5VSTBY

KEY_A
KEY_B
KEY_C

2
F

5VSTBY 5VSTBY

5VSTBY 5VSTBY

12VSTBY

5VSTBY

5VSTBY

5VSTBY

VGNSTBY

3139 243 31947 2005-04-12

EN 36

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Front: Front Panel

F212 D3

6201 A2
6202 C1
6203 C2
6204 C2
F200 B1
F201 A1
F202 B1
F203 C1
F204 D1

IO0

F205 D1
F206 D1
F207 C3
F208 C3
F209 C3
F210 D3
F211 D3

3

123

A

B

C

D

E

6200 A1

2208 B2
2209 D1
2400 E2
3200 A2
3201 B1
3202 B2
3204 D2
3205 D2
3206 D1

12

A

B

C

D

E

1202 B1
1300 C3
1301 D1
1401 E1
1402 E3
2200 A1
2201 A2
2202 A2
2203 A3
2204 B1
2205 D2
2206 D2
2207 B2

n001

3022

F210

21C-483XZB

3026

R
57

2023

8022

p
001

GND

702

2

GND

p001

2206

470p

6
0
23

R5
7

n001

GND

4022

GND

1023

R57

GND GND GND

470R

DNG

F206

3204

GND

F205

6

F212

1

3

2

5

4

1026

2
1
C

-483XZB

JPJ1127-01-0020

1301

9
0
22

2
1
C

-483XZB

0026

GND

n
0
01

0022

n0
0

1

F208

3200

10K

F200

GND

F201

470p

F207

4

2205

S4B-PH-K

1401

1
2
3

5401-042-101-92

1
2
3
4

1402

3205

470R

GND

GND

F204

GND

GND

GND

2026

21C

­4
8
3XZB

1022

V5
2
u01

1n0

2400

GND

GND

GND

YKF51-5362

1

2

3

Y

4

C

56

1202

F211

4026

21C

-483

XZB

2022

n01

F203

F209

1
2
3
4
5
6
7
8
9

GND

1

1300

B9B-PH-K

F202

5ESD 5ESD5ESD

5ESD 5ESD

Y

C

AL

AR

CVBS

5ESD

5VSTBY

3139 243 31947 2005-04-12

EN 37

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Layout: Front Panel (Top View)

FrontPanel_Topview_31947_3355.pdf 2005-07-15

EN 38

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Front: Standby

3

54132

51

1303 C4
2300 D2
6300 D2
6301 D3
F300 C2
F301 C2
I300 C4

DC0

42

D

A

B

E

1302 C2

E

C

A

B

C

D

I300

1303

F301

EVQ11L05R

0032

GND

F300

2n2

0036

8V6C-483XZB

1
2

8V6C-483XZB

1036

S2B-EH

1302

3139 243 32017 2005-04-12

Layout: Standby (Top View)

FrontPanel_Topview_hmc1_32017_3355_02.pdf 2005-07-15

EN 39

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Digital: Back-End Processor

5

4

3

2

1

0

11
12
13
14
15

ATAPI_DATA

ATAPI_ADDR

ATAPI

DIOR

DIOW

DMAACK

RESET

0
1
2
3
4

DMARQ

INTRQ

IORDY

6
7
8
9
10

GPIOEXT33

AO_D

GPIO6

0

1

SCLK

MCLKO

IEC958

FSYNC

3

2

1

0

AI_MCLKO

SCLK

FSYNC

AO_MCLKI

AI_MCLKI

AI_D

CS8

CS9

AO

AI

GPIOEXT32

1394

1394_PHY_DATA

1394

1394

LINK_ON

PHY_CLK

PHY_CTL0

PHY_CTL1

0
1
2
3
4
5
6
7

LPS

LREQ

1
2
3
4
5
6
7
8
9

lVGPIOEXT<0:7>

VO_D

VI_D

VI_CLK0

5
6
7

2

0

4

VO_CLK

1

3

VI_VSYNC0|PEC

0

SCL

ADR

0
1
2 SDA

WC

DAC5_OUT

DAC6_OUT

TDI

TDO

TMS

TRST

TCK

DAC1_OUT

DAC2_OUT

DAC2_OUT_B

DAC3_OUT

DAC4_OUT

DAC4_OUT_B

HMST_CS0_8BIT HMST_ALE

HMST_DTACK

0
1
2
3

5

4

HMST_CS

HMST_GPIO

HMST_UWE

0
1
2
3

5

4

HMST_OE

LWE

MA6:15
MDATA0:15

HMST_AD

MA22:26

MA1:5

HMST_ADDRHI

0
1
2
3
4

HMST_ADDRLO

PCMCIA_IOR

PCMCIA_IOW

HMST_UDS

HOST_PO_0

0
1
2
3
4

HMST_LDS

HMST_RST

HMST_WR

HOST_OC_0

HMST_WAIT

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SDRAM_DQ

SDRAM_DQS

0
1
2
3

SDRAM_DQM

SDRAM_A

SDRAM

CAS
CKE

CLK0

CLK0

CLK1

CLK1

WE

RAS

3

2

0
1

0
1
2
3
4
5
6
7
8

9
10
11
12
14
15
16
17

21
22
23
24
25
26
27
28
29
30
31

SDRAM_VREF

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

GPIOEXT39

CS6

GPIOEXT40

CS7

SIO

CS10

GPIOEXT24

GPIOEXT25

GPIOEXT37

GPIOEXT38

GPIOEXT42

GPIOEXT41

SPI_MISO

UART1_RX

SCL

SDA

SIO_SPI_CS0

SIO_SPI_CS1

SIO_IRTX1

SIO_IRRX

SIO_UART2_RX

SIO_UART2_TX

SIO_UART1_CTS

SIO_UART1_RTS

SIO_SPI_CLK

SIO_SPI_CS2

SIO_SPI_MOSI

SIO_UART1_TX

GPIOEXT35

BYPASS_PLL

CKI

MCONFIG0

CLKX

CLK0_DAC

DMINUS_0

DPLUS_0

AGND GND GND

F
ER

V

AVDD VDD

0_
DD
V

A_
B
S
U

VDD25

0
0
V5
_
SA
I
B

DDVD_CAD

0_
D
DV
_
CA
D

3_
D
DV
_
CA
D

D
DVFER

VDDP

DD
V

LAT

X

S
S
VL
AT

X

0
_D

N
G
A
_B
S
U

SSVF

E
R

1
S
S
V
D_C

A
D

GND

2120 B6
2121 F9
2122 F9
2123 F9

1 9 10111213

FC: DA0

Communication (COM)

Audio (AUD)

E

A

B

C

D

F

G

H

I

A

B

C

2128 F10
2129 F10
2130 F10
2131 G8
2141 G9

D

E

F

G

H

I

1101 B10
1111 E10
2101 B10
2102 B11
2105 G12
2108 F1
2109 F2

2158 I11
2161 I12
2162 I12
2171 I10

2345678

2182 I12
2183 I12
2191 I12
2199 E11
3101 B1

12345678910111213

3132 C9
3133 C9
3134 C9
3135 C9

)AOV( golanA tuptuO oediV

2124 F9
2125 F9
2126 F10
2127 F10

3136 C9
3137 C9
3138 C9
3139 D9
3141 E7

2142 G9
2143 G10
2144 G10
2145 G10
2146 G10
2147 G10
2151 H10
2152 I10
2153 I10
2154 I10
2155 I10
2156 I10
2157 I11

3155 E7
3156 E8
3161 A11
3162 B12

IEEE1394 Link - Physical (LNK)

2172 I10
2173 I10
2174 I10
2175 I10
2176 I10
2181 I11

3168 G13
3169 H13
3171-1 G1
3171-2 G1
3171-3 G1

3102 B1
3103 B1
3104 C1
3111 D5
3112 D6
3113 D6
3114 D6
3121 B6
3122 B6
3123 B6
3124 A9
3125 B9
3131 C9

3175-1 H1
3175-2 H1
3175-3 H1
3175-4 H1

FC: DM3

3177-4 I1
3178-1 I1
3178-2 I1
3178-3 I1
3178-4 I1

3142 E8
3143 E7
3144 E8
3145 E7
3146 E8
3147 E7
3148 E8
3149 E7
3150 E8
3151 E7
3152 E8
3153 E7
3154 E8

3184-2 G4
3184-3 G4
3184-4 G4
3185-1 H4

Back-end Front-end Interface (IDE)

3163 B10
3164 C10
3165 C10
3166 C10
3167 C10

3186-3 H4
3186-4 H4
3187-1 I4
3187-2 I4
3187-3 I4

3171-4 G1
3172-1 G1
3172-2 G1
3172-3 G1
3172-4 G1
3173-1 G1
3173-2 G1
3173-3 H1
3173-4 H1
3174-1 H1
3174-2 H1
3174-3 H1
3174-4 H1

3199 E11
5121 F9
5131 G8
5141 G9

Back-end Processor

Back-end SDRAM (BES)

3176-1 H1
3176-2 H1
3176-3 H1

3176-4 H1
3177-1 I1
3177-2 I1
3177-3 I1

5161 H11
5162 H12
5171 I10
5181 I11
6101 C3

3181-1 G4
3181-2 G4
3181-3 H4
3181-4 H4
3182-1 G4
3182-2 H4
3182-3 G4
3182-4 H4
3183-1 G4
3183-2 G4
3183-3 H4
3183-4 G4
3184-1 G4

F101 B6
F102 B6
F103 B6
T101 B1

)DIV( latigiD tupnI oediV

Back-end Flash (BEF)

3185-2 I4
3185-3 I4
3185-4 H4
3186-1 H4
3186-2 I4

3187-4 H4
3188-1 I4
3188-2 I4
3188-3 I4
3188-4 I4
3191 H8
3192 F12
3193 F12
3194 F12
3195 F12
3196 F12
3197 E12
3198 E12

T102 B1
T103 B1
T104 B1
T105 B1

5151 H10

7101-1 D5
7101-10 I7
7101-2 A5
7101-3 B12
7101-4 A2
7101-5 F7
7101-6 D2
7101-7 A8
7101-8 F3
7101-9 A12
7105 G12
7111-1 E12
7111-2 F13

T106 B1
T111 E11
T112 E11
T113 E11
T121 A11
T122 B11

n
0
01421

2

3137 10K

n0
0
1

55
12

4K7

3196

3192
10K

T103

22R 3183-118

n0
0
14512

100n2109

100n2120

3164 22R

2K23147

T101

1%1K2

3191

45

7

47R3173-4

3173-2 47R2

n0
0
16512

T102

T106

n
0
0192

12

3161
10K

Y1

N3
M4
M3
M2
N2

U3

R2

T2

W1

V2

T3

T1
R3

P1
P3
R1
R4
U1
W2

P4
P2
N4

ATAPI

Φ

V3
T4
V1
U2
U4

36

7101-6

DMN-8602

3172-3 47R

2K2

2K23149

3151

7

3155 2K2

3183-222R 2

A12

A17
B15
B16
B17

A14

B13A13

A15

B14

Φ

C14

D14

D13

C13

A16

n
0017

4
12

AUDIO

DMN-8602

7101-2

3622R 3183-3

K014013

3013

5913

K01

3142

8K6

2K2

u022

1812

2K23146

V61

5

3

4

BC847BS

7111-2

7

22R 3187-22

18

K01

47R3176-1

8

2013

3186-122R 1

22R3165

22R 3185-336

3123

10K

22R3124

n
00
125

12

J3

K1

J2
L2
L4
L3
J1
K4
K3
K2

7101-5

DMN-8602

PHY-LINK

Φ

J4

M1

N1

L1

n0015212

V0
5
u
22

1
412

2105
100n

n0
018

212

2K2

BLM18P

5161

3145

5

3171-4 47R4

2K23141

22R

BLM18P

5171

C9
B9

3169

C12
D12
A11

A10

A8

B10

C7
D8
C8
B8
D9

A9

D7
C10
B11
C11
D11
D10
B12

Φ

VIDEO

DMN-8602

7101-1

22R 3182-336

5181

BLM18P

36

47R3177-3

10K

3125

3186-227

U10

W8

22R

V12

W9
V8

Y9

W15

V14

U8

Y7

H3 H2

U6

Y8

Y3

Y11

Y5
Y4
Y6
Y2
W3

U9

V6
W12
W10

W5

U5

W4

V5

V4

V7

U7

W6

W7

Y10
W11
V10

U13
U12
Y14
W13
V13
U11
Y13

7101-7

DMN-8602

W14

Y12
V11
V9

B5

A5

A6

B7

A7

C6

B6

D6

Φ

HOST

INFC

JTAG

Φ

DMN-8602

7101-4

A1

A2

B4

A3

A4

DAC

10K3138

0n1

9912

47R3172-4 4 5

5141

BLM31

3186-322R 36

4

7

M24C16-RDW6

7105

1
2
3

6

5

8

47R27

EEPROM

Φ

(2Kx8)

V6
1

3178-2

3177-2 2 7

12
12

u0
33

36

47R

3187-322R

1

7111-1

BC847BS

2

6

10K

3194

3174-2 2 7
3174-1 1 8

47R
47R

3139 10K

n0
012

212

n0
0
1

64
12

36

n
001441

2

7

47R3171-3
47R3171-2 2

22R3122

22R 18

3181-1

BLM31

5121

n0012412

7K466

1
3

3174-3 3 6

1

2

3

4

47R

B4B-PH-K

1111

n
00
185

12

1101

AT-4913M5

K0113

1
3

183178-1 47R

3185-422R 45

p8
1

20
1
2

K011113

27

F103

3185-222R

2108 100n

3184-122R 18

K
012

3
13

3171-1 1 8

22R

47R

3168

47R273172-2

n0
0
13

5
12

3622R 3188-3

n
00
154

12

T121

5162

BLM18P

T112

18

27

3187-122R

22R 3181-2

3163
1M0

K
0
153

1
3

3177-4 47R45

T105

n0011912

47R36

18

3173-3

3182-122R

47R27

3175-2

18

T104

5

47R3177-1

3176-4 47R4

18

n0
0
17

5
12

45

3172-1 47R

22R 3181-4

n00

1

67
1
2

45

T111

47R3175-4

T113

22R 3188-118

36

47R3176-3

3173-1 47R18

6101

BAV99

1
51
2

V5
2
u
01

V
5
2u

0
1

1712

K012113

2K23143

22R 36

K014313

47R45

3181-3

3156

3174-4

2K2

2K23152

W19

Y19

U17

U16

V18

V15

U14

Y18

Y17

Y15

W16

V16

Y16

W18

W17

U15

SERIE-IO

Φ

7101-3

DMN-8602

K013113

3183-422R 45

BLM31

5151

100R

3199

C18

N17D16

N19

1K0

3198

K18
K17
J19

K19
H20
F20
D18

M20
J20
F19

A19
A20
B20
C19

M17

B19
C20

L19
L18
L17

G19
G18
G17
F18

N20

F17
E19
E18
E17
A18
B18

K20

E20
D20

M18
M19

H19
J17
J18
H18
H17
G20

R19
R18
T18
T20
V20
U19
W20

P20
N18

L20

7101-8

DMN-8602

R17
T19

U18
V19
U20
Y20
R20
P18
P19

P17

SDRAM

Φ

T122

3913

K01

22R 3187-445

3197
4K7

n0012612

2K2

n
0013

4
12

3154

3150 2K2

K012613

K016313

4522R 3184-4

3176-2 2 7

47R

n0
015

712

3148 2K2

2K2

3175-1 47R18

3144

2K23153

5131

BLM18P

7K47613

36

27

3184-322R

3184-222R

K
0
13

31
3

2712

n
0013712

n00

1

n0012812

n0013812

3121 22R

3175-3 47R36

22R 45

3182-222R 27
3182-4

K014113

F102

F101

3188-222R 27

K011013

45

3178-3 47R36

47R3178-4

n0011612

n00147

1
2

n
001131

2

4522R 3186-4

71T

71V

1C

2
E

2F

11
E

21
E

21T

11T

5L

5
M

9T

01T

9
E

01E

9
1D

3F

4F

7
1
D

61C

61J

61
K

6
1
L

61
M

4H

5J

5K

2
1
N

3

1

N

9H

01H

11
H

21
H

31H8J

2C1B

8M

9
M

01
M

8
H

11M

21M

3
1
M

8
N

9N

0
1
N

11N

0
1
K

11K

2
1
K

7
1
C

31K8L9L

01
L

11
L

21
L

3
1
L

2B

3
B

51C

9J

01J

11J

21J

31J

8K

9K

3
E

3
C

4
D

3D1D

4
C

4E

2
D

5
1D

5D

5C

G3

G2

SUPPLY

7101-10

DMN-8602

7101-9

DMN-8602

G1

E1

H1

F1

G4

MISC

Φ

p811012

n
00132

1
2

n0017212

n
00
1621

2

3188-422R 45

18

22R 3185-1

n
00103

1
2

VIP_SDA

5VBE

3V3BE

TRST#

TMS

TDO

TDI

TCK

3V3BE

SYSRST#

3V3R

3V3BE

3V3U

3V3BE

3V3V

3V3BE

1V8BE

1V8D

3V3BE

2V5S

3V3BE

3V3BE

3V3BE

3V3BE

3V3BE

3V3BE

3V3BE

3V3BE

EB3V3

VIP_SCL

U
3V

3

2V5S3V3P 1V8C

A3
V

3

2V5S

2V5BE

1V8C

1V8BE

3V3P

3V3BE

3V3A

3V3BE

5VBE

3V3A

5VBE

1V8D3V3V

R3
V

3

3139 243 31875 2005-04-15

EN 40

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Digital: Memory

19

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

VSS

VDD

0

A

D

5

2

4

RB

OE
CE

7

6

WE

3

1

RP

0

BYTE

2M-1 / 1M-1

NC

A-1

8

9
10
11
12
13
14
15

D

A

DQS

L
U

11

4
5
6

1
2
3

CK

DM

U

L

VREF

10

CK

4

BA

CS

512

2

CAS
WE

15

RAS

0

CKE

VSS

9

14

13

VSSQ

VDDQVDD

7

1

0

NC

6

12

8

1

0

10
11

AP

3

7
8
9

EN
C1

1D

EN
C1

1D

D

A

DQS

L
U

11

4
5
6

1
2
3

CK

DM

U

L

VREF

10

CK

4

BA

CS

512

2

CAS
WE

15

RAS

0

CKE

VSS

9

14

13

VSSQ

VDDQVDD

7

1

0

NC

6

12

8

1

0

10
11

AP

3

7
8
9

F

G

2262 C12
2263 C12

2268 D12

2270 E12
2271 E12
2272 E12

2233 B8
2234 B8

2276 F12
2277 F12
2278 F12

2236 B10
2237 B10
2238 B10
2239 B10
2240 D8

3265-1 D12

7211 C6
7231 C9
7292 F4
7293 H4
7294 H7
T201 D3
T202 D3

3269-1 E12
3269-2 E12

FC: DM2

FC: DM1

2252 A12
2253 B12
2254 B12

11

2267 D12

2256 B12
2257 B12
2258 B12

G

H

2261 C12

A

B

C

D

E

2292 F4
2293 H4
2294 F8

8

3263-1 D12
3263-2 C12

5201 B2
5291 F2
7201 C2

3269-4 D12
3271-1 E12
3271-2 E12

3273-3 E12
3273-4 E12

12

3269-3 D12

3273-2 E12

13

A

B

Back-end Flash (BEF)

3259-1 C12
3259-2 C12
3259-3 C12
3259-4 C12
3261-1 C12

45678

2259 C12

2291 G2

2266 D12

2241 D8
2251 A12

2260 C12

2255 B12

2201 D1
2202 D2
2203 D3

3281-3 F12
3281-4 F12

2211 B5

3284 G12
3285 G12
3286 G12
3294 H8
3295 I6
3296 H8
4291 H6

2219 B7
2220 D4

3251-1 A12

2283 G12

2281 F12
2282 F12

C

3

H

I

3277-4 F12
3281-1 F12

3283 G12

3275-1 F12
3275-2 F12
3275-3 F12
3275-4 E12
3277-1 F12

3277-2 F12
3277-3 F12

4292 H6
4293 H6

2221 D4

3253-3 B12

2265 D12

2231 B8
2232 B8

12 13

2235 A10

23

2264 C12

Back-end SDRAM (BES)

3251-2 A12

2273 E12
2274 E12
2275 E12

3253-2 B12

2269 D12

91011

3263-3 C12
3263-4 C12

1

3265-2 D12
3265-3 D12
3265-4 D12
3267-1 D12
3267-2 D12
3267-3 D12
3267-4 D12

2284 G12

3257-3 B12
3257-4 B12

3255-3 B12
3255-4 B12
3257-1 B12

7

Memory

1

3261-2 C12
3261-3 C12
3261-4 C12

3253-4 B12
3255-1 B12
3255-2 B12

564

3251-3 A12

D

E

F

2204 D4
2205 D3

3251-4 A12

2212 B5
2213 B5
2214 B5
2215 A7
2216 B7
2217 B7
2218 B7

3253-1 B12

3271-3 E12
3271-4 E12
3273-1 E12

109

2

4294 I8

3281-2 F12

3257-2 B12

12

73

72

64

11

100n2235

38
40
42
44
30
32

13
14
10

28

15

26

29
31

34
36
39
41
43
45

33
35

9

23
22
21
20
19
18
8
7

47

24

6
5
4
3
2
1
48
17
16

6

[FLASH]

2Mx8/1Mx16

7294

M29W160ET70

25

3265-3 47R3

47R3265-2 2 7

47R3286

43

84

66

6

21

258546

21

51

1

81

33

3

9

5
1

55

1
6

49

16

14
17
19
25
43
50
53

23

47

63
65

5
7

8
10
11
13
54
56

20

45
44

46

24

2

4

57
59
60
62

31
32
35
36
37
38
39
40

26
27

22

16Mx16

SDRAM

29
30

28
41
42

n001

7231

DDR

Φ

2022

2257 100n

27

18

3267-2 47R

5

3263-1 47R

3269-4 47R4

3277-4 47R45

45

3281-4 47R

100n2275

47R3257-4 4 5

3257-3 47R36

45

3273-4 47R

2215 100n

2272 100n

18

1022

V
05u2

2

47R3277-1

2259 100n

100n2282

100n2258

47R3284

2254 100n

2284 100n

47R3267-1 1 8

3283 47R

47R3275-2 2 7

36
27

3271-3 47R

47R3271-2

2213 100n

50V22u

2211

100n2237

2236 100n

10K3295

3263-3 47R36

47R3263-2 2 7

16
15
14
13
12

02

6
7
8
9

01

11

1

19
18
17

74LVC573ADB

7293

2
3
4
5

5

47R3251-4 4

100n2253

47R3263-4 4 5

18

3271-1 47R

T202

47R3261-1 1 8

3259-4 47R45

3275-4 4 5

18

47R

47R3259-1

47R3281-1 1 8

3647R3273-3

2218 100n

2273 100n

100n2216

2261

2260

100n

100n

47R3261-3 3 6

47R3277-3 3 6

3277-2 47R27

BLM31

5201

18

5

47R3273-1

47R3271-4 4

2294 100n

18

3255-1 47R

3253-3 3 6

100n2238

27

47R

3253-2 47R

36

14
13
12

02

3251-3 47R

9

01

11

1

19
18
17
16
15

2
3
4
5
6
7
8

7292

74LVC573ADB

47R3259-3 3 6

27

n
0
0114

22

3259-2 47R

n0010222

T201

47R3269-3 3 6

2269 100n

2268 100n

100n2267

2217 100n

100n2219

2292 100n

27

4292

3261-2 47R

n0011222

3253-4 47R45

4294

192

2

BLM18P

5291

7

V
5
2
u
01

47R3251-2 2

4291

100n2266

100n2271

100n2270

n
0
01

0
422

2262 100n

V61u033

3022

100n2239

100n2212

100n2293

100n2283

18

3251-1 47R

4K73296

2265 100n

2264 100n

2747R3255-2

100n2252

2251 100n

n0015022

21

2
5

85

46

21

3

9

51

5
5

16

49

438466

6

25
43
50
53

23

47

51

1

81

33

8
10
11
13
54
56

20

16

14
17
19

2
4

57
59
60
62
63
65

5
7

37
38
39
40

26
27

22

45
44

46

24

29
30

28
41
42

31
32
35
36

SDRAM
16Mx16

Φ

DDR

7211

2234 100n

47R3253-1 1 8

1

CN

PVIN7

5QDDV

VREF 4

VSENSE 3

VTT 8

7201

LP2995

AVIN6

D
N
G

2

47R3281-3 3 6

3281-2 47R27

3294 4K7

100n2263

47R3255-4 4 5

3255-3 47R36

47R3269-1 1 8

45

3267-3 3 6

3267-4 47R

47R

100n2278

2276 100n

18

2277 100n

3257-1 47R

3269-2 47R27

100n2233

3273-2 47R27

2281 100n

3285 47R

100n2274

47R18

2231

22u 50V

3275-1

2232 100n

45

n
0
01

4
02

2

47R3265-4

36

4293

3275-3 47R

2256 100n

100n2255

45

3261-4 47R

18

100n2214

3265-1 47R

3257-2 2 7

47R

3V3F

BA{BA(6:21)}

3V3F

3V3F

SYSRST#

2V5D

VTT 2V5D

SYSRST#

3V3F

3V3F

2V5D

2V5D

VTT

2V5BE

2V5D

2V5D 2V5D

3V3F

3V3F

3V3BE

3139 243 31875 2005-04-15

EN 41

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Digital: IEEE 1394 Physical Layer

0
1

R

0
1

FILTER

DGND

LKON

D

PC

CTL

DDVLLPSH_D

N
G

AGND

DVDD

DNGLLP

AVDD

TPA+
TPA-

TPB+
TPB-

7

6

5

4

3

2

1

0

1

0

LREQ

SYSCLK

RESET

PD

TPBIAS 0

1

C

2

XO

ISO

LPS

TESTM

SE

SM

CPS

XI

3310-2 E9

3310-1 E9

3308 F7

3311-1 E9

3310-4 E9

3311-2 E9

3312 E9

3307 F7

3311-4 F9

3311-3 E9

3304 G8
3305 E8
3306 F7

T305 E7
T306 E7
T307 E7
T308 F7
T309 E7
T310 F5
T311 F7
T312 E7
T313 E7
T314 E7
T315 F5
T316 F5
T351 E5
T352 E5

E

FC: ME0

D

F

G

H

I

1351 D5
2301 D6
2302 D6

214

)YHP

(
t
r
o
ps

na
r
T

- l
aci
sy
h

P 4
931E

E
EI

3756

IEEE1394 Link - Physical (LNK)

2343 G9
2351 D5
2352 E5
2361 E5
3301 E5
3302 F5
3303 G8

3310-3 E9

2305 D7

2307 D7

2303 D6

IEEE1394 Physical Layer

2304 D6

2321 G5
2341 G9

8 9 10 11 12 13

1 11 12

B

C

D

E

13

A

2345678910

3313 E9
3314 D9
3315 E9
3321 F5
3322 G5
3331 F5
3332 F5

T304 E7

3341 F9
3342 F9
3343 F9
3344 F9
3345 G9
3351 E5
3360 E5
3361 E5
3362 E5
4361 E5
5301 C6
7301 D6
T301 E7
T302 E7
T303 E7

F

G

H

I

A

B

C

2306 D7

1K03301

T304

T352

T301

4K7

3310-2

27

3310-3

4K736

4K7

3310-4

45

1K03362

100n

25V10u

2301

2307

100n2305

100n2304

100n2302

2351

2352 33p

33p

680R

T316

3306

4361

T314

3304 10K

T311

T310

2433

%
1R

65

T307

7K
4

2233

T351

10K3303

3302 10K

2306 100n

%1R65

143

3

680R3307

1K03361

100R3321

1232

3332

n001

3331

1%750R

1%5K6

T308

T312

%
1

1
K
5

54
33

p022

34
3
2

T306

T305

3433

%1R

65

T303

T302

3308 680R

3314 4K7

4K73315

4K73312
4K73313

3311-1

4K718

3311-2

27

3311-3

4K736
4K7

45184K7

3311-4

3310-1

4K7

3360 1K0

2303 100n

T315

T313

24

1

22

30
29

28
27

31

42

43

16
17
1812

14

04

33
34

37

23

74

12

44

54

38
39

94

19

13

48

15

4
5
6
7
8

9
10
11

41646223

63

52

53

20

2

3

TRANCEIVER

ARBITER

Φ

1-PORT CABLE

TSB41AB1PHP

7301

100n2361

T309 22R3305

5301

BLM18P

0M1

1533

%
1R65

4
4
33

24M576 AT-49

1351

1432

3V3I

3V3I

LNK_DATA(0)

LNK_DATA(1)

LNK_DATA(2)

LNK_DATA(3)

LNK_DATA(4)

LNK_DATA(5)

LNK_DATA(6)

LNK_DATA(7)

LNK_CTL1

LNK_CTL0

3V3I

LNK_CLK

0u1

3V3I

3V3I

3V3BE

3V3I

3V3I

3139 243 31875 2005-04-15

EN 42

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Digital: Video Input Processor

CS

I2CA

C

DDV81A_4HC

D
D
V33A_3

H
C

DDV81A_3HC

D
D
V
3
3A_2

H
C

Y

GPIO<0:14>

RED

GREEN

BLUE

VBLK

FSO

D
N
G
81A_2HC

D
N
G3
3A
_
2HC

DNG81

A
_3H

C

D
N
G
33A_3HC

DNG81A_4HC

F
ER_DNG81

A

Φ

SH_

D
N
G

DNG

A

DNG81

A
_1H

C

DNG33A_1HC

PWDN

IOVDD

DD
V

81A

_
1HC

DATACLK

DVDD

DDV33A_4HC

DNG

8
1A_

L
LP

IOGND

SCL

VI_1_A
VI_1_B
VI_1_C

VI_2_A
VI_2_B
VI_2_C

VI_3_A
VI_3_B
VI_3_C

VI_4_A

DDV81A_LLP

RESETB

SDA

XTAL1

XTAL2

DDV81A_2HC

DDV3

3
A_1HC

VS

HS

GLCO

FSS

FID

C_9

C_8

C_7

6

5

4

3

2

1

AVID

0

FER_DDV81A

9

8

7

6

5

4

3

2

1

0

INTREQ

DNG33

A
_4H

C

DGND

2473 E6
2474 E6
2475 E7
2476 E6
2477 E6
2478 E7
2479 E6
2480 E7
3400 D10
3401 C10
3407 D6

8 9 10 11 12 13

A

B

C

D

E

2423 E2
2424 E2
2425 E2
2426 E3
2427 E3
2431 E2
2432 F2
2433 F2
2434 F2
2435 F2
2453 D5
2461 C6
2462 D6
2471 E6
2472 E7

2401 C2
2402 C2
2403 C2
2404 C2
2411 D2
2412 D2
2413 D2
2414 D2
2415 D2
2421 E2
2422 E2

12345678910111213

1234567

3488-2 F11
3488-3 F11
3488-4 F11
3492-1 E11
3492-2 F11
3492-3 F11
3492-4 F11
4471 E6
4472 E6
4473 E5
4474 E6

Video Input Digital (VID)

)AIV( golanA tupnI oediV

Video Input Processor

F

G

H

I

A

B

C

D

E

F

G

H

I

1461 C6

T403 F10
T404 F10
T405 F10
T406 F10
T407 F10
T408 F10
T409 F10
T411 E10
T412 E10
T461 C7
T462 D7

3408 D6
3452 D5
3453 D5
3454 E10
3455 D5
3461 C7
3471 F4
3472 F4
3473 F4
3474 F5
3475 F5
3476 F5
3477 F5
3478 F5
3479 F5
3480 F5
3481 E11
3482 E11
3484 F11
3486 F11
3488-1 F11

4475 E6
4476 E5
4477 E6
4478 E6
4479 E5
4480 E6
4481 E11
4486 E11
5401 C2
5411 D2
5421 D2
5431 E2
7401 C7
F401 D10
F402 D10
T400 E10
T401 F10
T402 F10

600R

270R

4479

4475

600R

4478

%1

R
5767

4
3

%1R5

7
17
4

3

T411100n2479

T407

T409

T405

T408

T406

52
51
50
47
46
45
44
43

8
9

16
17
18

23

73

74

75

54
53

16

77

6
7

33

34

28

29

80
1
2

7

35

37

18

72

30

93

94

2
6

83

8
4

40

722324

65

86

1314

5
5

76

71

70
69
66
65
64
63
60

59

58

57

11

655

1

419102

42

52

22

12

3
1 21

62

36

97

87

3

4

01

TVP5146PFP

7401

100n2474

2477 100n

%1R5

74

743

n0013142

0M11643

4481

T404

T403

2K23400

n
0
0
1

2242

T401

100n2453

T400

3492-4 4 5

T412

22R

2473 100n

T462

2743

T461

600R

%1R57

4472

V52

100n2478

u01

1342

n
0
0
1414

2

V52

1042

u01

1142

V52u01

5401

BLM18P

n
0
012042

R578743

BLM18P

%1

10K3481

5411

n0013242

22R

3408

22R

3407

F402

F401

%1R5

7
5

743

4486

%1R

5
7

0
843

246133p

4474

n001

4
342

5431

n0
0
1

BLM18P

2342

27

n
0
0172

4
2

18

22R3492-2

3492-1 22R

n0015242

n0014242

100R

3455

V52u01

1242

3492-3 22R36

n0013342

100n2476

22R3482

22R

4477

3484

5

3401

2K2

3488-4 22R4

n0016242

4473 680R

n0015142

n
0014

0
42

2475 100n

%1

R
5737

4
3

n0
0
1534

2

BLM18P

34542K2

5421

36

22R27
22R3488-3

18

3488-2

22R3488-1

%1R5777

4
3

T402

n0013042

4471

10K3452

270R

100n2480

4480

n
0
0
12142

100n2472

2471 100n

3453

100R

%1R

5
79743

22R

3486

246233p

1641

4476 600R

3V3BE

3V3D2

3V3BE

3V3A2

SYSRST#

2
A
8V1

2
A
3V

3

VID_RST#

2D3V3

3V3D2

VIP_SCL

VIP_SDA

2D8V1

2
A
8V1

3V3D2

1V8BE

1V8BE

1V8A2

1V8D2

3139 243 31875 2005-04-15

EN 43

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Digital: Interfaces

COM

OUTIN

FB

OUT

COMP

VREFVCC

INH

SYNC

GND GND_HS

1

2

IN

1

2

3

OUT

Video IO

USB

T600 I1
T601 I1
T605 H8
T606 I8
T607 I8
T608 I8
T611 H11
T612 H11
T613 H11
T614 H11
T615 H11
T616 I11

Power supply

ATAPI

)
Y
HP(

t
r
o
ps

na
r
T

- la

c

isy

h
P 49

3
1EE

E

I

Audio IO

T572 F1
T573 F1
T574 F1
T575 F1
T576 F1
T577 F1
T578 F1
T579 G1
T580 G1
T581 G1
T582 G1
T583 G1
T584 G1
T585 G1
T586 G1

T587 G1
T588 G1
T589 G1
T590 H1
T591 H1
T592 H1
T593 H1
T594 H1
T595 H1
T596 H1
T597 H1
T598 H1
T599 I1

FC: DIA

)
A

I
V
( golanA t

u
pn
I

oed

i
V

)AOV( gol

a
n
A

tu

p
tuO o

e
diV

T541 B13
T542 B13
T543 B13
T544 B13
T545 B13
T546 B13
T547 C13
T551 D12
T552 D12
T553 E12
T554 E12
T555 E12
T556 E12
T557 E12
T558 E12
T559 E12
T560 E12
T561 E12
T562 E12
T563 E12
T564 E12
T565 E12
T566 F12
T567 F12
T568 F12
T569 F12
T571 F1

IEEE1394

T510 D1
T511 D1
T515 A2
T516 C7
T517 F6
T518 A8
T519 A8
T520 A8
T521 A8
T522 B8
T523 B8
T524 B8
T525 B8
T526 B8
T527 B8
T528 B8
T529 C8
T530 C8
T531 C8
T532 C8
T533 C8
T534 C8
T535 C8
T536 A13
T537 A13
T538 A13
T539 A13
T540 A13

FC: DP2

)M

O
C(
n

o

it
ac
in
u
m
moC

3584-4 I2
3695 F6
4523 D6
4581 H2
5511 D2
5518 B2
5521 C2
5525 C6
6501 C4
6502 C4
6505 C6
6506 C7
6521 D6
6595 F6
7501 H6
7515 A2
7521 C3
7522 D5
7595 F5
T501 C1
T502 C1
T503 C1
T504 C1
T505 C1
T506 C1
T507 C1
T508 D1
T509 D1

FC: ME0

3573-4 F2
3574-1 F2
3574-2 F2
3574-3 G2
3574-4 G2
3575-1 G2
3575-2 G2

3575-3 G2
3575-4 G2
3576-1 G2
3576-2 G2
3576-3 G2
3576-4 G2
3577 G2
3578 G2
3579-1 H2
3579-2 H2
3579-3 H2
3579-4 H2
3580 H2
3581 H2
3582 H2
3583 H2
3584-1 H2
3584-2 H2
3584-3 I2

FC: MU0

Communication

3539 A11
3540 A11
3541 B11
3542 B11
3543 B11
3544 B11
3545 B11
3546 B11
3552 D9
3553 E9
3556 E9
3557 E9
3560 E9
3561 E9
3562 E9
3563 E9
3564 E9
3565 E9
3566 F9
3567 F9
3568 F11
3571 F2
3572 F2
3573-1 F2
3573-2 F2
3573-3 F2

Interfaces

2576 B9
2577 B9
2578 B9
2579 B9
2580 C9
2581 C9
2582 C9
2583 H2
2584 C9
2585 C9
2586 C9
2595 F5
2596 F5
3501 I6
3502 H6
3503 I8
3504 I8
3505 I8
3506 I8
3521 C6
3522 D6
3523 C6
3524 D5
3525 D5
3526 D6
3528 D5
3537 A11
3538 A11

2526 D7
2527 D4
2528 D5
2529 C5
2541 C11
2542 C12
2543 C12
2544 C12
2545 C12
2546 C12
2552 F9
2553 F9
2556 F10
2557 F10
2560 F10
2561 F10
2562 F10
2563 F10
2564 F10
2565 F11
2566 F11
2567 F11
2570 A9
2571 A9
2572 A9
2573 B9
2574 B9
2575 B9

FC: DI4

2345678910111213

A

B

C

D

E

F

G

H

I

A

B

C

D

E

)M

OC
( n

oi
ta

ci
n
um

moC

2523 D2
2525 D6

2508 B5
2511 D2
2512 E2
2513 E2
2515 B2
2516 B2
2517 B2
2518 C2
2519 C2
2520 C2
2521 D2
2522 D2

)DUA( oi

d
uA

)
E
D

I
( ecaf

re
tn
I
dne

­t
n
o
rF

dn
e

-kc

a
B

12345678910111213

1

F

G

H

I

1501 C1
1502 H9
1512 H12
1521 A9
1522 A9
1536 A13
1551 D12
1571 F1
2501 I7
2502 I7
2503 I6
2505 B4
2506 B4
2507 B5

2581

22p

22p

2580

2579

22p

22p

2578

T559

T614

T558

T556

T557

CHASSIS1 CHASSIS2

22p

2572

n
0
0
19

1
5
2

5518

BLM31

1
15

2

V6
1u

0
3
3u

0
22

815

21

2
5
2

V
6
1u

0
2
2

V61

36

T607

3574-3 33R

T605

T608

T606

1
2
3
4

B4B-PH-K

1502

T555

2571

22p

22p

2570

T527

n0010

2
52

2056

067TAB

067

TA
B

1056

T562

3506

T561

15K

7

T509

T565

33R3574-2 2

3574-1 33R18

22p

2596

T502
T503

T501

22R3557

T569

p
22

2
55

2

T510

T522

T615

3563 22R

p
22

2
65

2

n0017152

13

CHASSIS3 CHASSIS4

LD29150DT25R

7515

2

T525

T526

067T

AB

6056

T523

T539

T537
T538

%1

K
2
1

2253

5K6

3523

1%

3
2
54

3556 22R

3583 680R

T532

T520

T518

p221452

22R3541

p222452

T567

p223452

T508

T511

T506
T507

T504
T505

7
8
9

22R3545

1

10
11
12

2
3
4
5
6

B12P-PH-K

1501

T541

TSL0809

5525

T542

42
SS

12
5
6

T544

T533

T524

p
22

3
65

2

T529

36

T528

7

33R3573-3

3573-2 33R2

33R3573-1 1 8

5152

V
5
2
u01

n0016152

6
7
8
9

18
19

2

20
21
22

3
4
5

1

10
11
12
13
14
15
16
17

HLW22S-2C7

1536

5056

067TAB

n001

6
252

INP

4

NC

1

OUTP

%
1

R04

2

1253

7595

NCP303LSN30

5

CD

3

GND

2

T553

7K4

8253

8
252

%
1

n22

T536

p
02272

52

5252

V61u033

28
29

3

30

4
5
6
7
8
9

19

2

20
21
22
23
24
25
26
27

1

10
11
12
13
14
15
16
17
18

8

6

1521

HLW30S-2C7

Φ

4

5

7

9

3

1

2

7521

L5973D

n
0
0
1315

2

n0012152

T535

T554

n00

1

2252

BLM31

5521

3542 22R

6595 BAS316

7
K4

59
63

n
0
01595

2

33R3578

T579

5
6
7
8
9

p226452

15
16
17
18
19

2

20

3
4

1

10
11
12
13
14

1551

HLW20S-2C7

T543

T540

T545

T519

22R3539

3540 60R

n00

120

52

n
00130

52

T585

T599

T583
T584

T582

T611
T612

T552

T590

T551

33R3579-4 4 5

27

33R3579-2

T587

3572 33R

T530

T531

T572

T588

T571

3581 4K7

3580 33R

T601

T594

22R3560

4K73577

3501 10K

10K3502

T591

T592

T589

22R3503

n
0
0
1705

2

n
0
0
18

052

n
0
0
1505

2

n
0
016052

T568

T534

BLM31

5511

n0
01

3
25

2

p
22

4
652

T574

22R3564

T573

DNG

2

3

5

OC_

6

7

8

TPS2041D

7501

EN_

4

1

4581

45

3552 22R

33R3584-4

T598

T597

p227652

p
22

6
652

6

T613

3584-3 33R3

33R3584-2 2 7

3584-1 33R18

33R45

33R3576-3 3 6

3576-4

2575

22p

T547

3546 22R

33R18

T560

3579-1

p
22

7
552

T517

BC847B

7522

2586

22p

22p2583

T563

7K48653

T566

V6
1
u0
22

1052

22R3504

3565 22R

p
22565

2

3567 22R

4
5
6

78

22R3566

BM06B-SRSS-TBT

1512

1
2
3

T600

22R3537

3538 22R

T564

6

3561 22R

3579-3 33R3

3505 15K

33R3582

22p

2574

2573

22p

p
22

1
652

p
22

0
652

p2
2

65
5
2

22n

2529

5253

6
2
53

0K1

0
K
1

22p

22p

2585

2584

6
7
8
9

22p

2582

19

2

20
21
22
23
24

3
4
5

1

10
11
12
13
14
15
16
17
18

1522

HLW24S-2C7

22R3562

2577

22p

T616

22p

2576

T578

T577

T586

T575

10K3571

T546

T521

45T576 3573-4 33R

T593

T596

T595

4

40

5
6
7
8
9

3

30
31
32
33
34
35
36
37
38
39

2

20
21
22
23
24
25
26
27
28
29

10
11
12
13
14
15
16
17
18
19

1-440094-2

1571

1

22R3553

p22355

2

3576-2 33R27

3576-1 1 84533R

36

33R3575-4

27

3575-3 33R

8

33R3575-2

3575-1 33R1

33R3574-4 4 5

3524

1K0

22R3543

p224452

3544 60R

T515

p225452

T516

T581

HOSTRST#

T580

5V

5V

3V3BE

5VBE

SYSRST#

5VBE

5V

5VBE

3V3BE

HOSTRST#

5VBE

5V

1V8BE

2V5BE

3139 243 31875 2005-04-15

EN 44

3139 785 3093x

7.Circuit Diagrams and PWB Layouts

Layout: Digital-Main Part (Top View)

Digital_Topview_3355_02.pdf 2005-07-15

EN 45

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Layout: Digital-Main Part (Bottom View)

Digital_Bottomview_3355_02.pdf 2005-07-15

EN 46

3139 785 3093x

7.

Circuit Diagrams and PWB Layouts

Notes:

EN 473139 785 3093x 8.

Circuit- and IC description

8.1. Front Board (Panel – Display + Key)

8.1.1. General

This board consists of the following parts:

• Slave μP

• Frontend (Audio & Video)

• VFD Heater voltage Generator

8.1.2. Slave μP (IC 7105: UPD16316GB)

The core element of the Front Display + Keyboard is the slave
μP. It runs on a 5V supply and is responsible for the following
functions:

• Interface with the Domino chip on the Digital Board

• Evaluation of the keyboard matrix within Front board

• Decoding the remote control commands from the infra-red

receiver

• Activation and control of the display

• Timer Wake-up activation

It runs on two clock frequencies namely:

• 5MHz for normal operation

• 32.768KHz for the real time clock

8.1.3. Interface to the Domino chip

It communicates with the Domino Host on the Digital board
via a 6-wire synchronous serial interface. The Host is always
the master to generate the communication clock to the slave
μP irrespective of the direction of data transfer.

8.1.4. Evaluation of the keyboard matrix

A key matrix is used on the Front board. The slave μP does
the key scanning with FIP9 - FIP24 (pin 23-26 and 29-40) as
output and KEY_A - KEY_C (pin 41-43) as input. Each key is
assigned a key code based on the output and input ports, and
the slave μP will do the evaluation by getting the key codes.

8.1.5. IR receiver and signal evaluation

The IR receiver on the Front Board contains a selectively
controlled amplifi er as well as a photodiode. The photo-diode
changes the received infrared transmission to electrical
pulses, which are then amplifi ed and demodulated. On the
output of the IR receiver, a pulse sequence with TTL-level,
which corresponds to the envelope curve of the received
IR remote control command, can be measured. This pulse
sequence is fed into the slave μP for further processing via
pin 13.

8.1.6. Vacuum Fluorescent Display [1203: HUV-08SS65T]

The VFD is fully controlled and driven by the slave μP.

8.1.7. VFD Heater Voltage Generator

The oscillator circuit provided by [5100, 2101, 2102 & 7100]
provides the necessary sine wave signal for transistors [7101,
7102 & 7103] to generate the 50% duty-cycle 48KHz AC
square-wave signal for the fi lament of the VFD.

8.1.8. Timer Wake-up activation

During the Standby mode, the slave μP provides a wakeup
call (POWER_CTL-line switches to high) to the Domino Host
on the Digital Board. It will then starts up and asks for the
wake-up reason.

8. Circuit- and IC description

8.2. Analog Board

8.2.1. General

The pc board consist of the following parts:

• Fan Control (OPTION)

• Power Supply Unit

• Tuner Frontend

• Audio ADC/DAC

8.2.2. Fan Control

The Laser on the OPU of the drive is very sensitive to
temperature. A fan control circuit [7802 & 7803] is built into
the board as a provision. The fan is ON when the set is in
active mode, and OFF when the tray opens. When the set is
in Standby mode, the fan is switched off. The control of the
fan is coming from the Digital Board.

8.2.3. Power Supply Unit

This power supply functions on a circuitry combination
of a SMPS control IC [7400], switching FET [7401] and
transformer [5400] as a switched-mode power supply
(SMPS).
Feedback control is provided by the IC 7404, which compares
the 5V-output voltage via voltage dividers [3421, 3422 &
3423] with an internal 2.5V reference voltage. The output
voltage is fed to an optocoupler [7403] that provide the
insulation between the primary and secondary parts as a
current value into pin 3 of the IC 7400.

The following are the various supply lines provided:

• 3V3SW to CU, DAC_ADC, Digital Board

• 5V to IOA, IOV, CU, CINCH, MSP, DIGIO and

FV

• 5N to MSP (provision only) and Digital Board
(provision only)

• 5VE to Basic Engine

• 5V_BE to Digital Board

• 5NSTBY to IOA, CINCH and DAC_ADC

• 5VSTBY to IOA, IOV, FV, MSP, DAC_ADC, Front

Board

• 8VSTBY to MSP

• 12V to Digital Board

• 12VSTBY to CU, IOV, DAC_ADC, Front Board

• 12VE to Basic Engine and Digital Board (provision

only)

• 33VSTBY to FV

• VGNSTBY to Front Board

Standby modes:

In Standby mode, the STBY control line is low, switching off
the 3V3SW, 5V, 5N (provision), 5VE, 12V and 12VE supply
and thus reducing the power consumption.

EN 48 3139 785 3093x8.

Circuit- and IC Description

8.2.4. Tuner Frontend [1100 : TMQZ2]

It has a RF IN for antenna connection and RF OUT which
provides a RF loop through for connection to the TV.

The Frontend ( Tuner & IF-demodulator ) is controlled by I

2

C
(SCL_5V- and SDA_5V-) lines coming from the Domino Host
on the Digital board.
Complete video processing is done in this unit and the video
output (CVBS) is taken out from the [VID_OUT] pin via a
transistor as CVBS_TV-line to the Video I/O circuitry. The
audio-IF component SIF1 is taken out from the [SIFOUT] pin
for the demodulation by the Multi-sound processor (MSP).

Audio demodulator

The sound demodulation is done by the MSP3415 [7500],
which is also fully controlled via I2C bus by the Domino Host.

The audio signals are available at pin 26 and pin 27 and fed
as AFER- & AFEL- line to the audio I/O for further processing.

EN 493139 785 3093x 8.

Circuit- and IC description

8.2.5. Audio routing

Figure 8-1 Analog Audio In / Out Overview

Analog Audio In / Out Overview

Scart2

6

3

2

1

AudInL

AudInR

AudOutL

AudOutR

6

3

2

1

AudInL

AudInR

AudOutL

AudOutR

Scart1

Tuner

SIF1

OUT2L

OUT2R

AKILL

AKILL

AKILL

AKILL

OUT1L

OUT1R

OUT1R

OUT1L

AFER

AINFR

AINFL

AINFR

AINFL

RSA1

RSA2

AIN2R

AIN2L

AIN1R

AIN1L

ARDAC

AFER

AFEL

AFEL

AIN2L

AIN2R

SIF1

SDA_5V

SCL_5V

AIN_SEL1

ARDAC

ALDAC

BKILL

BMUTE

ALDAC

Dig.Audio Out

from digital board

AL

AR

1

UDA1361TS

ADC

A_DATA

to dig. board

3

ALADC

ARADC

15

CS4351

DAC

VOR

VOL

18

ARDAC

ALDAC

D_DATA

from dig. board

LH

Logic

1

3

5

1

109

LL

HL

MSB LSB

HEF4052

4

5

15

L

H

L

H

HHLHLL

HL

HH

3

1

11

14

12

13

2

6

MSB/LSB

POS.7302

MSP3415G

2

I2C Control

8

9

12

13

26

27

31

30

37

38

41

40

Q.Peak Det

Source select

Demodulator

DACM_L

DACM_R

SC1_OUT_L

SC1_OUT_R

POS.7500

0dB

0dB

LH

Logic

1

3

5

1

109

LL

HL

MSB LSB

HEF4052

2

4

12

L

H

L

H

HHLHLL

HL

HH

3

5

15

11

14

13

1

6

MSB/LSB

POS.7303

AIN_SEL0

0dB

0dB

AIN1L

AIN1R

AOUT2R

AOUT2L

ARDAC

ALDAC

DVDR3355_Eur_Audio IO dd wk527

POS.7704

POS.7703

from Domino Host

(Digital Board)

MUTE

DKILL

POWER_FAIL

AKILL

BKILL

REAR OUT

(CVBS/YC)

FRONT IN

(CVBS/YC)

19

14

BMUTE

AMUTE

DAOUT

AMUTE

MUTE

MUTE

from Domino Host

(digital board)

EN 50 3139 785 3093x8.

Circuit- and IC Description

The sound processing is always done in stereo (that means
separate left- and right- channel) and the complete switching
is realized by using HEF4052 which is a dual four-to-one
multiplexer and MSP3415G which is a multi-sound processor.

a) Scart 1 – Output path

The multiplexer [7303] selects either signals from the Scart 2
Input (AIN2L/AIN2R) or the Audio DAC (ALDAC/ARDAC) as
the output source for Scart 1 (AOUT1L/AOUT1R).

b) Scart 2 – Output path

The MSP [7500] selects either signals from the Scart 1 Input
(AIN1L/AIN1R), the Audio DAC (ALDAC/ARDAC) or the
Tuner Frontend as the output source for Scart 2 (AOUT2L/
AOUT2R).

c) Digital audio-out path

In addition, a digital output (DAOUT) coming from the
Digital board is passed through a 6-fold inverter [7900]
for performance reasons (noise reduction, jitter, …) and
transformer (level correction, ground isolation,…) to the digital
out cinch socket at the rear.

d) Record path

The record-selector [7302] selects either signals from the
Scart 1 Input (AIN1L/AIN1R), Scart 2 Input (AIN2L/AIN2R),
Front Cinch (AINFL/AINFR) or the MSP (AFEL/AFER)
and routes to the audio ADC (ALADC/ARADC) for record
purposes. The switch is controlled via RSA1 and RSA2
signals coming from the MSP.

8.2.6. Audio ADC/DAC

The conversion of analog audio signals from the record­selector [7302] outputs (ALADC/ARADC) is done via
UDA1361TS [7704]. This IC can process input signals up to
2Vrms by using external resistors in series to the input pins.
All required clock signals are generated on the digital board
and only the audio data (A_DAT-line) are routed to Digital
board for further processing.

The transformation of digital audio back into analog domain
is done by CS4351 [7703]. All necessary clock signals
are coming from the digital board and digital audio data
(D_DATA0-line) are converted into analog signals (pin 15 and

18). The output signals from the audio DAC part (ALDAC/
ARDAC) are directly routed to the rear cinch sockets. To
avoid plops and any other audible noise on the output muting
circuits are implemented for each channel.
Muting for the various other output lines are done via AKILL
& BKILL-lines which is a combination of the D_KILL from
the Digital board and POWER_FAIL from power supply and
AMUTE & BMUTE (digital silence mute) from DAC-part.

EN 513139 785 3093x 8.

Circuit- and IC description

8.2.7. Video-routing

Figure 8-2 Analog Video In / Out Overview

Analog Video In / Out Overview

DGO4

DGO2

DGO1

NJM2267M

Pos 7606

Pos 7210

DENC

From digital board

to VIP

To digital board

VideoIn

VideoOut

R/C_In

G

Bin/out

FastBlk

8SC2

to CU

SlowBlk

CVBS_FIN

CVBS

Y/C

Y_FIN

FrontIN

C_FIN

CVBS_REAR

D_CVBS

D_Y

D_C

D_VR

D_YG

D_UB

CVBS_TV

D_Y

D_CVBS

A_UB

A_YG

VideoIn

VideoOut

R/C_Out

G

Bout/Cin

FastBlk

SlowBlk

D_CVBS

D_Y

CVBS

Y

C

A_UB

A_YG

A_VR

A_VR

CRout

ROUT

CVBS_RE

YCVBSOUT1

CVBSOUT2

GOUT

BOUT

FBOUT

CVBS_TV

CVBSIN1

YCVBSIN2

D_CVBS

D_Y

RCIN

D_C

GIN

RCIN

BIN

D_YG

D_VR

D_UB

FBIN

CVBS_FIN

Y_FIN

C_FIN

CVBS_TV

FBIN

to CU

From CU

DigOUT1

(pin 42)

0V

2.2V

5V

Video Aspect

Ratio detection

& AV switching

12V6V0V

8SC2_1

8SC2_2

to Digital

Board

Video Aspect

Ratio detection

Scart FS

In/Out

loop through

DGO2

DVDR3355_Eur_Video IO dd wk527

EN 52 3139 785 3093x8.

Circuit- and IC Description

(1) analogue CVBS / YC and RGB/YUV
(2) analogue CVBS, YC, RGB/YUV

DDR SDRAM

16M X 16Bit

TO/FROM FRONTEND PART
ATAPI

VIP

TVP5146

1394

TSB41AB1

DOMINO

DMN-8602

7101

1FH VIDEO

OUT

(2)

DIG. AUDIO OUT

I

2

S A UDIO OUT

I

2

S A UDIO IN

1FH VIDEO IN

(1)

I2C

7401

ITU656

CLOCK

7304

1512

For DV-in version only

FROM POWER SUPPLY

5V 12V3V3

1394

CONNECTOR

FLASH
16M Bit

7211/7231

7294

13.5MHz

Figure 8-3 Domino block

A matrix switch STV6618 [7210] controlled by the Domino
Host via I

2

C-bus is used for Video I/O switching. All used
outputs excluding pin 21 (Y/CVBS-REC) have a 6dB­amplifi cation and a 75 ohms-driver-stage inside. This IC also
includes several digital outputs, which are used for switching
purposes on the Analog board.
This matrix switch routes the selected inputs to the correct
output lines for TV viewing and further processing in the
Digital board.

The record selector inside the switch selects between the
inputs from Tuner Frontend (CVBS_TV), CVBS Scart1
(CVBSIN1), CVBS Scart2 (CVBSIN2) or D_CVBS from
the DENC (on Digital board). The output signal CVBS_RE
together with the other signals CVBS_FIN, Y_FIN & C_FIN
from the Front and RCB from Scart2 are routed directly to the
VIP (on Digital board) for further processing.

The signals D_C and D_Y are fed through [7606] (6dB
amplifi cation) and D_C via transistors [7213 & 7212] as driver
to the S-Video output socket. Likewise the signal D_CVBS is
fed through [7606] (6dB amplifi cation) to the rear CVBS cinch
socket.

8.3. Digital Board

The Digital Board is based on the highly integrated LSI
‘Domino’ BGA chip (Ball Grid Array), DMN-8602. This IC has
an on-chip ATAPI controller and integrates an analog video
encorder, and provides build-in support for non-simultaneous
progressive and interlaced video output. A 1394 link layer
function is also integrated so a simple external physical layer
device is required. The DMN-8602 also has a set of integrated
USB Physical Layer Interface.
The board encodes and multiplexes analogue video and

digital uncompressed audio (I

2

S) into an MPEG2 stream. This
MPEG2 stream is formatted for recording by the DVD+RW
engine. In the playback, the board will decode the MPEG2
video into analogue video. In addition, a DV stream can be
received via IEEE 1394 (i-Link), and transformed to MPEG2
format.

8.3.1. Record Mode

EN 533139 785 3093x 8.

Circuit- and IC description

FRONTEND INTERFACE

VIP

TVP5146

DOMINO

DMN-8602

7101

7401

7301

1934 PHY

24.576 MHz

14.31818MHz

13.5 MHz

7211

SDRAM

7231

SDRAM

150 MHz

Figure 8-4 DIMINO_CLOCK

The Domino chip has a complex system, which is needed to
support the processes running at different frequencies such
as video decoding, audio decoding or peripheral I/O devices
etc. To ensure a synchronous initialization of all the registers
and state machines, all the PLLs are switched to their default
frequency 27MHz.
Then when the booting control unit is correctly initialized and
once it has captured all the booting parameters, it sets the
PLLs to its functional frequencies. Thanks to a clock blocking
mechanism, the frequency switching is glitch free.

System clocks:

• DMN-8602 (7101, pin E1 and F1): 13.5 MHz provided by
the x’tal 1101

• DMN-8602 1394-LINK (7101, pin L1): 49.152MHz
provided by 1394-PHY

• TVP5146 (7401, pin 74 and 75): 14.31818MHz provided
by x’tal 1461

• SDRAM (7211 and 7231, pin 45 and 46): 150MHz
provided by the DMN-8602

• TSB41AB1PHP IEEE 1394 PHY IC (7301, pin 42 and

43): 24.576MHz provided by x’tal 1351

Video Part

The analogue video input signals CVBS, YC and RGB are
routed via the board to connector 1521 and sent to Video
Input Processor, TVP5146P [7401].
The digital video input signals from the DV-in on the Front
board are routed from connector 1521 via the IEEE 1394 PHY
IC [7301] to the Domino chip [7101].

The Video Input Processor encodes the analogue video to
digital video stream (CCIR656 format). The output stream,
named VID_D (9:0), is then routed to the Domino chip. This
IC encodes and decodes the digital video stream into / from
MPEG2 format.

Audio Part

I

2

S audio is sent from the Analog board to the Domino chip

via connector 1536.
The Domino chip compresses the I2S audio data into an

MPEG1-L2 / AC3 audio stream.

Front-end I2S

The Domino chip interfaces directly to the basic Engine via

ATAPI connector 1571.
It buffers the data streams that are coming from (or going to)
the Basic Engine.
In the Domino chip, the video MPEG2 stream and the audio
AC3 stream are sent to the basic Engine for recording
through ATAPI bus.

8.3.2. Playback mode

During playback, the data from the Basic Engine is going
directly to the Domino chip via ATAPI interface. The Domino
chip has the following outputs:

• Analogue video CVBS, YC and RGB outputs on
connector 1521

• I2S audio (PCM format) on connector 1536

• SPDIF audio (digital audio output) on connector 1536

• Progressive Scan output connector 1522 (Not for

European version)

8.3.3. Basic Engine Interface

The Digital board is equipped with an IDE bus (ATAPI) for
connecting to the Basic Engine.

8.3.4. Clock Distribution

EN 54 3139 785 3093x8.

Circuit- and IC Description

Reset concept Digital board

The rest circuitry [7595] takes cares that the different devices
on the digital board are boot-up in the correct order. At power
on the reset circuitry provides the following resets (delay τ1):

• SYS_RST# to the Domino chip [7101] and Flash Memory
[7294]

The Domino chip then generates other reset signals (delay

τ2) via its GPIOs:

• VID_RST# to reset the VIP [7401]

• LINK_RST# to reset the IEEE1394 DV PHY IC [7301]

• IDE_RST# to reset Basic Engine

8.3.8. I/O Connector

Audio IO Connector (item 136)

The Audio In/Out (AIO) connector is used to interchange
digital audio signals between the Analog and Digital board

Video IO Connector (item 1521)

The Video In/Out (VIO) Connector is used to interchange
analogue video signals between the Analog and Digital board

DMN-8602

Basic Engine

VAD8041

Delay t

3

VIP (TVP5146)

Delay t

2

PDI1394P25BD

Delay t

2

FLASH MEMORY

POWER ON

RESET & LOW

VOLTAGE

DETECTION

NCP303LSN30

IC7595

HOSTRST

5V Supply

FRONT

MICROPROCESSOR

RSTn

SYSRST#

LNK_RST#

VID_RST#

IDE_RST#

Figure 8-5 DOMINO_RESET

8.3.5. Power Supply

The Digital board is not powered in standby mode. The
control signal STBY on the analog board will enable the PSU
and power the digital board.

• STBY = Low: the digital board is in powered down
standby mode

• STBY = High: the power supply to the digital board is
enabled.
The 3V3, +5V and +12V come from the PSU, while the
following voltages are generated in the digital board:

• 1.8V core voltage is generated on the board by a 2A
switching step down voltage regulator [7521]

• 2.5V supply for the SDRAM is generated by an ultra fast
low dropout linear regulator [7515]

• 1.25V DDR termination supply is generated by regulator
[7201]

8.3.6. Memory

• FLASH IC7294: this memory contains the boot
parameters and application fi rmware

8.3.7. Reset

EN 553139 785 3093x 8.

Circuit- and IC description

8.4 IC Description

8.4.1 Analog Board

IC7421 - TEA1507 - SMPS Control IC

BLOCK DIAGRAM

d

th

SUPPLY

MANAGEMENT

internal

supply

UVLO start

M-level

V

CC

1

2

3

GND

S1

CTRL

FREQUENCY

CONTROL

VOLTAGE

CONTROLLED

OSCILLATOR

LOGIC

LOGIC

OVER-

VOLTAGE

PROTECTION

OVERPOWER

PROTECTION

short

winding

soft

start

S2

OVER-

TEMPERATURE

PROTECTION

SQ

R

UVLO

Q

MAXIMUM

ON-TIME

PROTECTION

POWER-ON

RESET

−1

VALLEY

TEA1507

100 mV

clamp

DRIVER

START-UP

CURRENT SOURCE

0.75 V

0.5 V

5

I

sense

6

DRIVER

MGU230

4

DEM

8

DRAIN

7

HVS
n.c.

OCP

LEB

blank

I

ss

2.5 V

burst
detect

Figure 8-6

PIN DESCRIPTION AND CONFIGURATION

SYMBOL PIN DESCRIPTION

V

CC

1 supply voltage

GND 2 ground

CTRL 3 control input

DEM 4 input from auxiliary winding for

demagnetization timing, OVP and OPP

I

sense

5 programmable current sense input

DRIVER 6 gate driver output

HVS 7 high voltage safety spacer, not

connected

DRAIN 8 drain of external MOS switch, input for

start-up current and valley sensing

handbook, halfpage

MGU231

TEA1507

1

2

3

4

V

CC

GND

CTRL

DEM

DRAIN

HVS

DRIVER

I

sense

8

7

6

5

Fig.3 Pin configuration.

EN 56 3139 785 3093x8.

Circuit- and IC Description

IC7500 - MSP34X5G - Multistand Sound Processor Family

BLOCK DIAGRAM

MSP34x5G

D_CTR_I/O-1

D_CTR_I/O-0

SC1_OUT_R

SC1_OUT_L

I2S_DA_OUT

DACM_R

DACM_L

26

27

16

30

31

8

9

ANA_IN+

ANA_IN-

I2S_DA_IN1

I2S_DA_IN2

ASG

SC1_IN_L

SC1_IN_R

SC2_IN_L

SC2_IN_R

MONO_IN

ADR_SEL

I2C_CL

I2C_DA

13

12

10

43

37

38

40

41

39

21

17

2

3

18

ADR_CL

I2S_WS

XTAL_IN

I2S_CL

XTAL_OUT

14

15

5

6

AVSS

44

AHVSS

AGNDC

DVSS

VREF1

VREF2

VREFTOP

RESETQ

STANDBYQ

TESTEN

TP

7

4

11

22

42

25

29

20

36

35

CAPL_M

34

DVSUP

AVSUP

AHVSUP

33 19

1

N.C.

23

24

28

32

N.C.

N.C.

N.C.

De-

Modulator

Pre-

processing

Source

select

Pre-

processing

ADC

ADC

Prescale

SCART

DSP
input
select

Loud-

speaker

sound

proeessing

Loud-

speaker

sound

proeessing

DAC

DAC

SCART
Output

select

X'tal

Oscillator

I

2

S

Control

I

2

C

Control

ADR BUS

Figure 8-7

EN 573139 785 3093x 8.

Circuit- and IC description

PIN CONFIGURATION

PMQFP44 package

CAPL_M

AHVSS

AGNDC

SC2_IN_L

SC2_IN_R

ASG

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

RESETQ

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

I2C_CL

NC

SC1_OUT_L

SC1_OUT_R

VREF1

NC

AHVSUP

DACM_L

DACM_R

VREF2

NC

NC

ANA_IN1+

ANA_IN−

TESTEN

XTAL_IN

XTAL_OUT

AVSUP

TP

D_CTR_I/O1

D_CTR_I/O0

ADR_SEL

STANDBYQ

MSP 34x5G

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

18

17

16

15

14

13

12

1234567891011

33 32 31 30 29 28 27 26 25 24 23

Figure 8-8

IC7703 - CS4351 - 192KHz Stereo DAC with 2vrms line-out

BLOCK DIAGRAM

PCM

Serial

Interface

Interpo lation

Filter with

Volume Control

Internal Voltage

Reference

External

Mute

Control

DAC

Serial Audio Input

Left and Righ t
Mute Controls

2 Vrms Line Level
Right Channel
Output

2 Vrms Line Level
Left Channel Outpu t

Reset

1.8 V to 3.3V

DAC

Register/Hardware

Configuration

Level Translator

Hard ware or I2C/SPI

Control Data

Multibit

ΔΣ Modulator

3.3 V

9 V to 12 V

Interpo lation

Filter with

Volume Control

Amp

+

Filter

Amp

+

Filter

Auto Speed Mode

Detect

Multibit

ΔΣ Modulator

Figure 8-9

EN 58 3139 785 3093x8.

Circuit- and IC Description

PIN DESCRIPTION AND CONFIGURATION

Pin Name # Pin Description

SDIN

1

Serial Audio Data Input (

Input

) - Input for two’s complement serial audio data.

SCLK

2

Serial Clock (

Input

) - Serial clock for the serial audio interface.

LRCK

3

Left / Right Clock (

Input

) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

MCLK

4

Master Clock (

Input

) - Clock source for the delta-sigma modulator and digital filters.

VD

5 Digital Power (

Input

) - Positive power supply for the digital section.

GND

6

16

Ground (

Input

) - Ground reference.

RST

10

Reset (

Input

) - Powers down device and resets all internal resisters to their default settings when

enabled.

VA

11 Low Voltage Analog Power (

Input

) - Positive power supply for the analog section.

VBIAS

12

Positive Voltage Reference (

Output

) - Positive reference voltage for the internal DAC.

VQ

13 Quiescent Voltage (

Output

) - Filter connection for internal quiescent voltage.

VA_H

17 High Voltage Analog Power (

Input

) - Positive power supply for the analog section.

VL

20

Serial Audio Interface Power (

Input

) - Positive power for the serial audio interface

BMUTEC
AMUTEC

14
19

Mute Control (

Output

) - Control signal for optional mute circuit.

AOUTB
AOUTA

15
18

Analog Outputs (

Output

) - The full scale analog line output level is specified in the

Analog Characteris-

tics

table.

Control Port
Definitions

SCL/CCLK

7

Serial Control Port Clock (

Input

) - Serial clock for the control port interface.

SDA/CDIN

8

Serial Control Data (

Input/Output

) - Input/Output for I2C data. Input for SPI data.

AD0/CS

9

Address Bit 0 / Chip Select (

Input

) - Chip address bit in I2C Mode. Control Port enable in SPI mode.

Stand-Alone
Definitions

DIF0
DIF1

8
7

Digital Interface Format (

Input

) - Defines the required relationship between the Left Right Clock, Serial

Clock, and Serial Audio Data.

DEM

9

De-emphasis (

Input

) - Selects the standard 15μs/50μs digital de-emphasis filter response for 44.1 kHz

sample rates

SDIN VL

SCLK AMUTEC

LRCK AOUTA

MCLK VA_H

VD GND

GND AOUTB

DIF1(SCL/CCLK) BMUTEC

DIF0(SDA/CDIN) VQ

DEM(AD0/CS

) VBIAS

RST

VA

1

2

3

4

5

6

7

8

9

10

11

12

17

18

19

20

13

14

15

16

EN 593139 785 3093x 8.

Circuit- and IC description

IC7704 - UDA1361TS - 96KHz Sampling 24-bit stereo audio ADC

BLOCK DIAGRAM

th

UDA1361TS

MGT451

1

V

INL

ADC

ΣΔ

DIGITAL

INTERFACE

DC-CANCELLATION

FILTER

DECIMATION

FILTER

CLOCK

CONTROL

3

16

V

INR

ADC

ΣΔ

13

DATAO

11

BCK

12

WS

6

SFOR

7

PWON

14

MSSEL

15

10

V

SSD

9

V

DDD

V

SSA

5

V

RP

4

V

RN

2

V

ref

8

SYSCLK

V

DDA

Figure 8-10

PIN DESCRIPTION AND CONFIGURATION

SYMBOL PIN DESCRIPTION

V

INL

1 left channel input

V

ref

2 reference voltage

V

INR

3 right channel input

V

RN

4 negative reference voltage

V

RP

5 positive reference voltage

SFOR 6 data format selection input

PWON 7 power control input

SYSCLK 8 system clock 256, 384, 512 or 768f

s

V

DDD

9 digital supply voltage

V

SSD

10 digital ground

BCK 11 bit clock input/output

WS 12 word select input/output

DATAO 13 data output

MSSEL 14 master/slave select

V

SSA

15 analog ground

V

DDA

16 analog supply voltage

handbook, halfpage

UDA1361TS

MGT452

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

INL

V

ref

V

INR

V

RN

V

RP

SFOR

PWON

SYSCLK

V

DDD

V

SSD

BCK

WS

DATAO

MSSEL

V

SSA

V

DDA

EN 60 3139 785 3093x8.

Circuit- and IC Description

8.4.2 Digital Board

IC7301 - TSB41AB1 - IEEE 1394a-2000 one port cable Transceiver/Arbiter

BLOCK DIAGRAM

Received Data

Decoder/Retimer

Link

Interface

I/O

Arbitration

and Control

State Machine

Logic

Bias Voltage

and

Current

Generator

Transmit Data

Encoder

Cable Port

Crystal

Oscillator,

PLL System,

and Clock
Generator

TPA+

CPS

TPA–

TPB+

TPB–

XI
XO

FILTER0
FILTER1

LPS

ISO

CNA

†

SYSCLK

LREQ

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

PC0
PC1
PC2

C/LKON

R0
R1

TPBIAS

PD

RESET

†

CNA output is only available in the 64-pin PAP package

Figure 8-11

EN 613139 785 3093x 8.

Circuit- and IC description

PIN CONFIGURATION

PHP package terminal diagram

14 15

AGND
AV

DD

R1
R0
AGND
TPBIAS
TPA+
TPA–
TPB+
TPB–
AGND
AV

DD

36
35
34
33
32
31
30
29
28
27
26
25

16

1
2
3
4
5
6
7
8
9
10
11
12

SYSCLK

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

PD

17 18 19 20

47 46 45 44 4348 42 40 39 3841

21

22 23 24

37

13

PHP PACKAGE

(TOP VIEW)

TSB41AB1

PLLGND

PLLV

FILTER1

FILTER0

LREQ

DGND

DGND

DV

TESTM

SE

SM

C/LKON

PC1

PC2

ISO

CPS

DV

RESET

XO

XI

DGND

LPS

PC0

DDDVDD

DD

DD

Figure 8-12

EN 62 3139 785 3093x8.

Circuit- and IC Description

PIN DESCRIPTION

TERMINAL

PHP NO.

TYPE I/O DESCRIPTION

26, 32, 36 Supply – Analog circuit ground terminals. These terminals should be tied together to the

low-impedance circuit board ground plane.

25, 35 Supply – Analog circuit power terminals. A combination of high frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001
μF. Lower frequency 10 μF filtering capacitors are also recommended. These
supply terminals are separated from PLLVDD and DVDD inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.

15 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset,

this terminal is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-kΩ series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:

a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI

(cable-power-status interrupt), or STOI (state-time-out
interrupt) register bits are 1 and the RPIE (resuming-port

interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.

N/A CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming

bias voltage.

20 CMOS I Cable power status input. This terminal is normally connected to cable power

through a 400-kΩ resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DV

DD

supply if application does not require it to be used.

2
3

CMOS I/O Control I/Os. These bidirectional signals control communication between the

TSB41AB1 and the LLC. Bus holders are built into these terminals.

NAME

AGND

AV

DD

C/LKON

CNA

CPS

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

4
5
6
7
8

9
10
11

CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the

LLC. Bus holders are built into these terminals.

EN 633139 785 3093x 8.

Circuit- and IC description

TERMINAL

PHP NO.

TYPE I/O DESCRIPTION

14, 46, 47 Supply – Digital circuit ground terminals. These terminals should be tied together to the

low-impedance circuit board ground plane.

21, 44, 45 Supply – Digital circuit power terminals. A combination of high-frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. Lower frequency 10 μF filtering capacitors are also recommended.
These supply terminals are separated from PLLVDD and AVDD inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.

38
39

CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form

a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1 μF ±10% capacitor is the only external
component required to complete this filter.

19 CMOS I Link interface isolation control input. This terminal controls the operation of output

differentiation logic on the CTL and D terminals. If an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should
be tied low to enable the differentiation logic. If no isolation barrier is implemented
(direct connection), or TI bus holder isolation is implemented, the ISO

terminal
should be tied high to disable the differentiation logic. For additional information
refer to TI application note

Galvanic Isolation of the IEEE 1394-1995 Serial Bus

,

SLLA011.

13 CMOS I Link power status input. This terminal monitors the active/power status of the link

layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-kΩ resistor either to the VDD supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than

2.6 μs (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6 μs). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. In the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. If the LPS input remains low for more than 26 μs (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.

48 CMOS I LLC request input. The LLC uses this input to initiate a service request to the

TSB41AB1. Bus holder is built into this terminal.

16
17
18

CMOS I Power class programming inputs. On hardware reset, these inputs set the default

value of the power class indicated during self-ID. Programming is done by tying
these terminals high or low. Refer to Table 9 for encoding.

NAME

DGND

DV

DD

FILTER0
FILTER1

ISO

LPS

LREQ

PC0
PC1
PC2

PD 12 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the

cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)

EN 64 3139 785 3093x8.

Circuit- and IC Description

TERMINAL

NAME

PHP NO.

TYPE I/O DESCRIPTION

41 Supply – PLL circuit ground terminals. These terminals should be tied together to the

low-impedance circuit board ground plane.

40 Supply – PLL circuit power terminals. A combination of high-frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001
μF. Lower frequency 10 μF filtering capacitors are also recommended. This supply
terminal is separated from DVDD and AVDD inside the device to provide noise
isolation. It should be tied at a low-impedance point on the circuit board.

33
34

Bias – Current setting resistor terminals. These terminals are connected through an

external resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std
1394-1995 output voltage limits.

37 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal

pullup resistor to VDD is provided so only an external delay capacitor is required for
proper power-up operation (see

power-up reset

in the Application Information
section). The RESET terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard
logic input, and may also be driven by an open-drain type driver.

23 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or
it may be tied to GND directly.

24 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal use this terminal should be tied to GND.

1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data

transfers, to the LLC.

22 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For

normal use this terminal should be tied to VDD.

30 Cable I/O

Twisted-pair cable A differential signal terminals. Board traces from the pair of
p

p

29 Cable I/O

positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.

28 Cable I/O

Twisted-pair cable B differential signal terminals. Board traces from the pair of
p

p

27 Cable I/O

positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.

31 Cable I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for

proper operation of the twisted-pair cable drivers and receivers, and for signaling
to the remote nodes that there is an active cable connection.

PLLGND

PLLV

DD

R0
R1

RESET

SE

SM

SYSCLK

TESTM

TPA+

TPA–

TPB+

TPB–

TPBIAS

XI
XO

42
43

Crystal – Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel

resonant fundamental mode crystal. The optimum values for the external shunt
capacitors are dependent on the specifications of the crystal used (see

crystal

selection

in the Application Information section). When an external clock source is
used, XI should be the input and XO should be left open, and the clock must be
supplied before the device is powered on.

EN 653139 785 3093x 8.

Circuit- and IC description

IC7401 - TVP5146PFP - 4x10bit DigitalVideo Decoder with microvision

BLOCK DIAGRAM

Composite and S-Video Processor

Y/C

Separation

5-line

Adaptive

Comb

Luma

Processing

Chroma

Processing

ADC1

ADC2

ADC3

ADC4

M

U

X

Component

Processor

CVBS/Y

C

Y/G

Pb/B

Pr/R

Gain/Offset

Color

Space

Conversion

C

Y

Output

Formatter

Y[9:0]

YCbCr

VBI

Data

Slicer

Copy

Protection

Detector

C[9:0]

Host

Interface

Timing Processor

with Sync Detector

VI_1_A
VI_1_B

VI_1_C

VI_2_A

VI_2_B

VI_2_C

VI_3_A

VI_3_B

VI_3_C

VI_4_A

CVBS/

Y/G

CVBS/

Pb/B/C

CVBS/

Pr/R/C

CVBS/Y

CVBS/Y/G

Analog Front End

Sampling
Clock

GPIO

FSS

HS/CS

VS/VBLK

FID

AVID

XTAL1

XTAL2

DATACLK

RESETB

GLCO

DRDGDB

FSO

PWDN

SCL

SDA

YCbCr

Figure 8-13

PIN CONFIGURATION

22 23

C_6/GPIO/RED
C_7/GPIO/GREEN
C_8/GPIO/BLUE
C_9/GPIO/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VI_1_B
VI_1_C

CH1_A33GND

CH1_A33VDD
CH2_A33VDD

CH2_A33GND

VI_2_A
VI_2_B
VI_2_C

CH2_A18GND

CH2_A18VDD
A18VDD_REF

A18GND_REF

CH3_A18VDD

CH3_A18GND

VI_3_A
VI_3_B
VI_3_C

CH3_A33GND

CH3_A33VDD

25 26 27 28

PFP PACKAGE

(TOP VIEW)

79 78 77 76 7580 74 72 71 7073

29

30 31 32 33

69 682167 66 65 64

34 35 36 37 38 39 40

63 62 61

VI_1_A

CH1_A18GND

CH1_A18VDD

PLL_A18GND

PLL_A18VDD

XTAL2

XTAL1

VS/VBLK/GPIO

HS/CS/GPIO

FID/GPIO

C_0/GPIO

C_1/GPIO

DGND

DVDD

C_2/GPIO

C_3/GPIO

C_4/GPIO

C_5/GPIO

IOGND

IOVDD

CH4_A33VDD

CH4_A33GND

VI_4_A

CH4_A18GND

CH4_A18VDD

AGND

DGND

SCL

SDA

INTREQ

DVDD

DGND

PWDN

RESETB

FSS/GPIO

AVID/GPIO

GLCO/I2CA

IOVDD

IOGND

DATACLK

Figure 8-14

EN 66 3139 785 3093x8.

Circuit- and IC Description

PIN DESCRIPTION

TERMINAL

NAME NUMBER

I/O

DESCRIPTION

Analog Video

VI_1_A

VI_1_B

VI_1_C

VI_2_A

VI_2_B

VI_2_C

VI_3_A

VI_3_B

VI_3_C

VI_4_A

80

1

2

7

8

9

16

17

18

23

I

VI_1_x: Analog video input for CVBS/Pb/B/C

VI_2_x: Analog video input for CVBS/Y/G

VI_3_x: Analog video input for CVBS/Pr/R/C

VI_4_A: Analog video input for CVBS/Y

Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)
can be supported.

The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 μF.

The possible input configurations are listed in the input select register at I2C subaddress 00h (see
Section 2.11.1).

Clock Signals

DATACLK 40 O Line-locked data output clock.

XTAL1 74 I

External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock
signal or a 14.31818-MHz crystal oscillator.

XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.

Digital Video

C[9:0]/
GPIO[9:0]

57, 58,
59, 60,
63, 64,
65, 66,

69, 70

O

Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also,
these terminals can be programmable general-purpose I/O.

For the 8-bit mode, the two LSBs are ignored.

D_BLUE 58 I Digital BLUE input from overlay device

D_GREEN 59 I Digital GREEN input from overlay device

D_RED 60 I Digital RED input from overlay device

FSO 57 I Fast-switch overlay between digital RGB and any video

Y[9:0]

43, 44,
45, 46,
47, 50,
51, 52,

53, 54

O

Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.

For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.

Miscellaneous Signals

FSS/GPIO 35 I/O

Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)
and the composite video input.

Programmable general-purpose I/O

GLCO/I2CA 37 I/O

Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control
(RTC) format.

During reset, this terminal is an input used to program the I2C address LSB.

INTREQ 30 O Interrupt request

PWDN 33 I

Power down input:
1 = Power down
0 = Normal mode

RESETB 34 I Reset input, active low

EN 673139 785 3093x 8.

Circuit- and IC description

TERMINAL

NAME NUMBER

I/O

DESCRIPTION

Host Interface

SCL 28 I I2C clock input

SDA 29 I/O I2C data bus

Power Supplies

AGND 26 I Analog ground. Connect to analog ground.

A18GND_REF 13 I Analog 1.8-V return

A18VDD_REF 12 I Analog power for reference 1.8 V

CH1_A18GND
CH2_A18GND
CH3_A18GND
CH4_A18GND

79
10
15
24

I Analog 1.8-V return

CH1_A18VDD
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD

78
11
14
25

I Analog power. Connect to 1.8 V.

CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND

3

6
19
22

I Analog 3.3-V return

CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD

4

5
20
21

I Analog power. Connect to 3.3 V.

DGND

27, 32, 42,

56, 68

I Digital return

DVDD

31, 41, 55,

67

I Digital power. Connect to 1.8 V.

IOGND 39, 49, 62 I Digital power return

IOVDD 38, 48, 61 I Digital power. Connect to 3.3 V or less for reduced noise.

PLL_A18GND 77 I Analog power return

PLL_A18VDD 76 I Analog power. Connect to 1.8 V.

Sync Signals

HS/CS/GPIO 72 I/O

Horizontal sync output or digital composite sync output
Programmable general-purpose I/O

VS/VBLK/GPIO 73 I/O

Vertical sync output (for modes with dedicated VSYNC) or VBLK output
Programmable general-purpose I/O

FID/GPIO 71 I/O

Odd/even field indicator output. This terminal needs a pulldown resistor.
Programmable general-purpose I/O

AVID/GPIO 36 I/O

Active video indicator output
Programmable general-purpose I/O

EN 68 3139 785 3093x8.

Circuit- and IC Description

IC7501 - TPS2041 - Power Distribution Switches

BLOCK DIAGRAM

OUT

OC

IN

EN

GND

Current

Limit

Driver

UVLO

Charge

Pump

CS

Thermal

Sense

Power Switch

†

†

Current Sense

Figure 8-15

PIN CONFIGURATION

1
2
3
4

8
7
6
5

GND

IN
IN

EN

OUT
OUT
OUT
OC

TPS2041

D OR P PACKAGE

(TOP VIEW)

Figure 8-16

EN 693139 785 3093x 8.

Circuit- and IC description

PIN DESCRIPTION

TERMINAL

NO.

NAME

D OR P

I/O

DESCRIPTION

TPS2041 TPS2051

EN 4 – I Enable input. Logic low turns on power switch.

EN – 4 I Enable input. Logic high turns on power switch.

GND 1 1 I Ground

IN 2, 3 2, 3 I Input voltage

OC 5 5 O Over current. Logic output active low

OUT 6, 7, 8 6, 7, 8 O Power-switch output

IC7521 - L5972D - 2A Switch Step Down Switching Regulator

PIN DESCRIPTION AND CONFIGURATION

PIN CONNECTION

PIN DESCRIPTION

N° Pin Function

1 OUT Regulator Output.

2,3,6,7 GND Ground.

4 COMP E/A output for frequency compensation.

5 FB Feedback input. Connecting directly to this pin results in an output voltage of 1.23V. An external

resistive divider is required for higher output voltages.

8 VCC Unregulated DC input voltage.

OUT

GND

GND

COMP

1

3

2

4

VCC

GND

GND

FB

8

7

6

5

D02IN1367

EN 70 3139 785 3093x8.

Circuit- and IC Description

IC7595 - NCP303 - Voltage Detector Series with Programmable Delay

BLOCK DIAGRAM

NCP303LSNxxT1

Open Drain Output Configuration

V

ref

2 Input

3 Gnd

5C

D

R

D

1 Reset Output

Figure 8-17

PIN DESCRIPTION AND CONFIGURATION

PIN CONNECTIONS AND

MARKING DIAGRAM

1

3

N.C.

Reset

Output

2

Input

Ground

4

C

D

5

xxxYW

(Top View)

xxx = 302 or 303
Y = Year
W = Work Week

Figure 8-18

EN 71

3139 785 3093x

P003

P001

P002

3139 249 2798 2005-03-02

Exploded View
of the Set

Figure 9-1

9.

Exploded View & Spare Parts List

EN 72

3139 785 3093x

9.

Exploded View & Spare Parts List

Spare Parts List

0002 3139 247 11131 MODULE DRIVE D4.3
0164 3103 601 20231 SPRING GROUND
0168 3103 601 20212 SPRING I-LINK
0196 3139 241 22761 COVER TOP DVDR3305
0228 3139 241 22791 PLATE REAR EU DVDR3305
0288 4822 532 60948 BUSH
0333 2422 549 00607 REMOTE CONTR DVDR3365/EU B
0333 2422 549 00611 REMOTE CONTR DVDR3355/DVDR3305
0336 4822 321 11499

MAINSCORD /02, /19, /51 only
0336 2422 070 98236 MAINSCORD UK 5A 1M8 VH BK B /05 only
0342 2422 076 00532 CBLE SCART 1M5 SCART 21P BK B
0345 4822 320 50377 CONNECT. CABLE PAL
0901 3143 027 62231 FRONT ASSY DVDR3365

/02, /19, /51 only

0901 3143 027 62261 FRONT ASSY DVDR3365 /05 only
0901 3143 027 62311 FRONT ASSY DVDR3355

/02, /19, /51 only

0901 3143 027 62331 FRONT ASSY DVDR3355 /05 only
0901 3143 027 62681 FRONT ASSY DVDR3305

/02, /19, /51 only

0901 3143 027 62701 FRONT ASSY DVDR3355 /05 only
0910 3143 027 61951 COVER TRAY ASSY DVDR3365
0910 3143 027 62351 COVER TRAY ASSY DVDR3355
0910 3143 027 62411 COVER TRAY ASSY DVDR3305
0920 3143 027 62251 FRAME ASSY
1001 3139 248 86731 DIGITAL BOARD DVDR3365

/05 only

1001 3139 248 84651 DIGITAL BOARD DVDR3365 /02, /19 only
1001 3139 248 86721 DIGITAL BOARD DVDR3365 /51 only
1001 3139 248 86691 DIGITAL BOARD DVDR3305 /05 only
1001 3139 248 86061 DIGITAL BOARD DVDR3305 /02, /19 only
1001 3139 248 86681 DIGITAL BOARD DVDR3305 /51 only
1001 3139 248 86711 DIGITAL BOARD DVDR3355 /05 only
1001 3139 248 85941 DIGITAL BOARD DVDR3355 /02, /19 only
1001 3139 248 86701 DIGITAL BOARD DVDR3355 /51 only
1003 3139 248 84591 FRONT BOARD DVDR3365
1003 3139 248 86561 FRONT BOARD DVDR3305
1003 3139 248 86291 FRONT BOARD DVDR3355
1004 3139 248 84751 STB BOARD DVDR 3355/DVDR3365
1004 3139 248 86551 STB BOARD DVDR 3305
1005 3139 248 84631 ANALOG BOARD DVDR3355/DVDR3365
1005 3139 248 86571 ANALOG BOARD DVDR3305
8002 3139 110 35631 FFC FOIL 22P/180/22P BD 1MMP
8003 3139 241 01081 FFC FOIL 20P/140/20P BD 1MMP
8004 3139 241 00241 FFC FOIL 30P/140/30P BD 1MMP
8007 3139 241 00591 CBLE HR 04P/220/04P LOADER SUP
8008 3139 241 01011 FFC FOIL 14P/180/14P BD 1MMP
8010 3139 241 00921 CBLE IDE 40P/280/40P IDE UL
8011 2422 076 00676 CBLE IEEE1394 DVDR3355/DVDR3365

EN 73

3139 785 3093x

10. REVISION LIST

Version 1.0
* Original Release

Version 1.1
* Add missing Exploded View drawing

10.

Revision List