! CCT diagram
! Component layout diagram
! Parts list
Main Board L971AY
! CCT diagram
! Component layout diagram
! Parts list
Display Board L972AY
! CCT diagram
! Component layout diagram
! Parts list
Transformers
! L924TX
! L925TX
! L931TX
Mechanical Assembly
! Mechanical and packing part list
Page 3
FMJ Dv29 Circuit description.
Overview
DV29
The
electronically and mechanically of the
is effectively a no compromise version both
DV79
.
The player is based around acclaimed Zoran Vaddis
V
chipset coupled to high specification
Wolfson
D to A
converters for all six audio output channels, also
featured in this design is a
HDMI
transmitter with
digital Video and a Audio output capable of Digital
Surround.
The DV29 and the DV79 use the same main board
and power supply stage but with many of the
components either upgrade or replaced with different
topologies, many of the critical audio/video
components with 0.1% tolerance within the DV29 and
we also have an extra toroid power supply for the
Audio stages.
Both the HDMI chip and Video encoder are of a higher
quality than those found inside the DV79.
Power supply board.
Non-switching
Mains power arrives at IEC inlet socket SKT1 and is
filtered by EMC choke LI and Y caps C3 and C4,
mains switch SW2a/b switches both Negative and Live
phases before the power reaches the mains select
switch at location
windings of the transformer
SW1
the switch allows the primary
TX1
to be wired in either
Parallel or Series configuration.
The Bridge rectifying Diode package at location D1
forms the basis of the conventional power stage and
supplies a VN35V6 (-35.6v) to the Switch mode
stage, transistor
DZ1
and allows for the series Zener diodes
DZ3
to supply the VN13V5 and VN19V rails.
TR1
is biased by 2v7 Zener diode
DZ2, DZ3,
We will also see a simple
A.C present circuit
this is
used for delayed output relay operation and fast relay
closure under interrupted supply conditions thus
preventing op-amp offsets from reaching the Audio
output sockets.
Switch mode
The switch mode supply is formed around the
Driver/Control chip
IC1
UC3843 (used in regulating
mode). The chip is referenced the –36.5V supply line
and the Digital ground DGND, the supply for the chip
is formed by the 12v Zener at location
DZ6
and can be
seen on Pin 7 as VCC. The power supply allows for
the switch-mode to be tied the to Audio sampling
frequency for any given compatible format see Fig 1.
is driven into the power supply via
Resistor R9 if no Sync is present the unit is set to free run at
xxxx due to the RT/RC network attached to Pin 4.
IC1
is running in regulated mode and monitors the voltage
output on the +5V and +3V3 D.C lines, the two voltages are
summed by
TR8
and Driven into the VFB and Comp inputs
of IC1, the Voltage is then regulated by changing the time
base of the PWM output at pin 6 (longer the time base the
lower the voltage), the
PWM switching frequency
is driven
into the switch-mode transformer by the high speed Nmos
device at position M1, R5 is used to sense the Current
across the gate of the Nmosfet and in the event of a short
circuit will safely shut the power supply down. We derive the
12v Mech supply from the output of M1 using the Ultra-fast
Diode at location D8 to rectify the PWM line.
The D.C outputs from the switch mode have extensive
switch mode noise removing filters these are seen as 100n
caps down to ground and Wire wound inductors in series
with the supply rail.
Power supply main board
All the power supply rails are supplied to the main board via
the 32 way FFC conector at location
CON1001
.
The Digital supplies from the switch mode stage of the
power supply arrive as
3V3D, +5VD
the Display board power supplies arrive as
–13.5V
all of the supplies have a second stage of
and
+12VD
–19V
we also see
-9V
,
and
implemented on the board to remove all traces of ultra-sonic
noise.
The 3V3D rail is the main 3V3 rail used to power the digital
circuitry; +5VD is used for all 5v Digital/Video supplies the
+12VD is used for Scart switching and to power the HDMI
circuit (not DV78).
The 1V8 rail is derived from the 3V3 rail and is regulated by
the adjustable regulator at location
REG1003
.
Page 4
The DV29 uses a separate isolated Toroid transformer
and Rectification stages based around Bridge rectifiers
DBR1000
C1048 and C1049 to supply the Analogue stages the
smoothed D.C output from this stage is fed
and L1015 (-).
Regulator
forms the Audio DAC supply.
Display board
The
these are simply passed through the main board,
being filtered on the way to prevent transmission of
noise through to the surrounding electronics. The
display takes the +5V, -19V, -13V5 and -9V the –13V5
and –9V form a floating 4.5V supply biased relative to
the –19V grid voltage.
Display Board
The main component of the Display board is
a Vacuum Florescent Display driver with keyboard san
and a serial data in/out interface.
The Chip receives display drive serial data from the
Vaddis V chip on the main board via Con1 on pins 12,
13 and 14 these will be seen a
data is used to drive the VFD a DOUT line interfaces
with the VADDIS V and supplies Keyboard Scan
information. The keyboard scan is a 6 x 4 matrix with
Key Source
the
Keyscan
Please see: above for power supply information.
Infra red
The
data and send the data to the Vaddis V on the main
board via transistors TR2 and TR3, LED 2 is used to
mix the rear panel RC5, this is covered in-depth within
the Coms and Video output section of this guide.
DBR1001
and
REG1001
appearing at S3, S4, S5, S6 and the
data returns appearing a K2, K3 and K4.
pick-up at location RXI receives RC5
and bulk smoothing caps
L1013 (+)
is fed from the +15V3 rail and
requires several supply voltages
IC1
this is
DIN, STS
and
CLK
this
Main Board electronics
Zoran Vaddis V.
The main processor/control chip on the main board is the
Zoran Vaddis V at location IC202, this is the latest
incarnation of the very popular Vaddis range of processors
and allows for a much lower component count when
compared to our earlier players as many of the playback
functions have moved onto the Vaddis V silicon.
Below you will see the
o 20 Bit digital video output for external Video
DAC’s and HDMI output stage.
o Decoded Analogue Video output (internal
DAC) used on the DV78 only.
Digital Audio output 3 data lines 6 channels for
o
internal L + R DAC’s and L + R + C + LS + RS
for DV79 and DV29 also used for HDMI for the
DV79 and DV29.
o SPDIF output.
o Internal display interface.
o Internal ATAPI interface.
o Internal IR interface.
o Serial in/out for RS232 DV79/DV29
A more detailed explanation of the Vaddis V and
peripheral components follows.
Vaddis Power
The Vaddis V is powered by two separate supplies the
Vaddis requires a 1.8v supply for the core, this is regulated
from the 3.3v rail by
supply power to the I/P – O/P ports of the chip.
ATAPI interface
CON203
connector. This is decoupled from the Drive via an array of
decoupling resistors as required by the ATAPI spec.
is an ATAPI interface on a 40 way IDE
major functions
REG1003
, the 3.3v rail is used to
of the Vaddis V
Page 5
Display Board interface
The display board interface is on the 16 way FFC flexi
foil connector at location
display also travels on the connector. There are 4 –
wires to interface with the VFD driver chip these are
seen as.
XFPDIN - Data to the display board
o
o FPDOUT - Data from the display board
o XFPCLK - Clock
o XFPSEL - Chip select
The above control lines are level shifted to 5v logic
from 3.3v levels by
levels required by the VFD drive chip.
The IR output from the Display board arrives as
IRRCV
wire-Ord with the re-panel remote input.
Digital Audio
The Digital audio leaves the chip 3 sets of data lines
labelled as.
Along with the ADAT line we will also see the
and
The Vaddis V also supplies a direct SPDIF output for
interfacing with ancillary processing equipment.
Digital Video
The Digital Video output from the Vaddis V consists of
the following signals:
The 20 bit wide bus
as follows.
Interlaced video mode: VIDP0 to 7 provide
multiplexed 8 bit Y, Cb and Cr data with VIDPO being
the Isb.
Progressive scan video mode: VIDP0 to 9 provide
10 bit multiplexed Cb, Cr data with VIDP0 being the
Isb.
being the Isb.
this is an open collector signal, which can be
o ADAT0 - Left and Right channel data
o ADAT1 - Left and Right surround
ADAT2 - Centre and Sub
o
ALRCK
o VIDPO to 19 - 20 Bit wide digital video data
o CLK_27M - 27 Mhz Video clock
o VSYNC - Vertical sync
o
VIDP10 to 19
as required for IS2 data conversion.
HSYNC - Horizontal Sync
CON202
IC200
(74HCT125) these are the
VIDP0
provide 10 bit Y data with VIDP10
. Power for the
to 19 provides video data
ABCLK
Flash/ SDRAM
IC203
is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at
135MHz
IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for
program storage (Player software).
The flash interfaces to the Vaddis V using the SDRAM bus
it may appear that the bus connects to the flash in a
random manner, however this is simply because the
Vaddis bus is multiplexed that way. The Flash will be
accessed at power up and the contents are copied to the
SDRAM the program will then be run from the SDRAM.
Series resistors are employed to isolate the flash bus from
the main SDRAM bus.
EEPROM
IC204
is a 8kBit (1K x 8) Serial EEPROM. This is used for
storage of non-volatile storage of player settings, region
settings and bookmark data.
Clocks
CLK27MV is the 27Mhz clock for video. It is used to
generate the 135Mhz clock for the Vaddis microprocessor
and DSP. The
Vaddis.
We run the Vaddis in
own master clock (see main clock section of manual) for
higher accuracy and improved performance across Audio
and Video.
RESET
IC201 is a reset generator chip that monitors the +3.3V rail
and ensures a reset signal
generated on power up, or if the mains power dips below
an operational level.
This signal is used to reset the Vaddis V and Flash micro
only. The Vaddis V line labelled as RESET* resets the
remaining circuitry of the player apart from the HDMI chip,
this has it’s own reset line labelled as HDMI_RESET this is
necessary if we require to reset the HDMI chip only (for
example when the HDMI sink is connected and then
disconnected).
Serial Port
The VADDIS V can interface with the external world via
RS232
the
Transceiver at location IC900, the serial data lines are
shown as SERIAL RX and SERIAL TX these lines allow
for direct control over the unit via RS232.
MCLKV
connector at location
is the audio master clock for the
PLL bypass
PWR_ON_RESET*
mode and generate or
is
CON900
and the RS232
Page 6
Fig 3. GPIO control signals from the Vaddis V
O/P
Single Name I/P-
PSUFSO-1 Output
ENABLE_AV Output
16/9 Output
9190INT* Input
GAIN_SCALING Output
ML_8740_0-2 Output
MC Output
MD Output
FSELE0-1 Output
MUTE* Output
DDC_SDA,DDC,SCL I/O
PROG_INT* Output
HDMI_RESET* Output
RESET* Output
Function
Control PSU Clock
divider
SCART control High
in normal operation
and low in standby
Scart 16/9
anamorphic control
line
Interrupt signal
from SII9190 HDMI
transmitter
High for HDCD gain
scaling
SPI load signal for
Audio DACs 0,1 and
2 (see note 1)
SPI clock signal for
DAC control
SPI data signal for
DAC control
Frequency select
generator
Active low audio
mute signal
12C bus for DDC
channel on HDMI
interface
High for Progscan
mode, Low for
interlaced mode.
Controls Sil9130
data mux
Reset signal for
HDMI transmitter
System reset
Clocks and SPDIF stage.
IC300
is a
SM8707E
clock generator IC. This IC is
sensitive to noise on it’s power supply, which causes
clock jitter for this reason we have a independent Low
dropout – low noise
based around the regulator at location
+3v3
power supply for the chip
REG300
.
X300
is a
27Mhz
crystal that
IC300
uses to generate
all the video and audio clocks required by the system
the crystal sits on the XTI and XTO pins of the chip,
the 27Mhz output at Pin 4 (MO2) is used to drive the
Vaddis chip directly bypassing the internal PLL.
The frequency of the audio master is dependent on
the on the current audio sample rate (I.e the sample
rate required by the format CD=44.1Khz and
DVD=48khz etc) and this is set by the system micro
FSLO
via the
22.5792Mhz or 24.576Mhz clock from frequency from
IC300 this may then be divided by 2 by the clock
and
FSEL1
this selects either the
divide chip at location IC306 depending on the status
of FSEL1. Therefore 4 clock frequencies may be
obtained to support all required audio samples rates.
Nand gate
IC303 is used to gate FSEL1 with
ENABLE_AV (which is low in standby mode) as such
when in standby mode the audio clock is disabled.
Clock Buffer
IC301 us used to buffer the audio master clock. The circuit
is arranged so that each device that requires the audio
master clock has it’s own driver these are seen as.
o MCLK_DAC0 - Pin 18
o MCLK_DAC1 – Pin 16
o MCLK_DAC2 – Pin 14
MCLK_VADDIS – Pin 3
o
o MCLK_HDMI – Pin 9
We also run the
Mute Line
from the Vaddis V
can be seen on Pin 12 and drives transistor
IC301
TR401
this
, the
transistor pulls the relays RLY400, RLY500, RLY600 to
ground and un-mutes the audio outputs.
IS2 Audio Data
IC302
and
IC309
are buffers for the 12S signals these
ensure that the signals travelling to the DAC’s are point to
point.
IC302
deals with the
ALRCK
and
ABCLK
and
IC309 the ADAT0,1,2 all signal are split into three
separate lines for the three stereo DACS.
PSU Clock Divider
IC304
the PSU clock is always either 44.1kHz or 48Khz (
1
within the power supply description section).
and
IC305
form a clock divide by 1, 2 or 4 to ensure
See fig
This circuit will also switch the PSUCLK off when
switching between sample rates (the PSU will free run
when the PSUCLK is not present).
SPDIF Output
The SPDIF output consists of
IC308
implemented as a
inline buffer and parallel output buffer. Gate A buffers the
signal so that the SPDIF line from the VADDIS sees fewer
loads and form a feed to the Optical output transmitter,
gates B,C and D drive the SPDIF in parallel so that we can
drive a 75ohm load adequately. The resistors at the output
of IC308 are arrange so that the output will be 500mV pk-
pk
when the output is terminated with a 75 ohm load at the
same time the output impedance of the circuit is 75ohms
as required by the Sony Philips Digital Interface
specification, the transformer at location TX301 electrically
isolates the SPDIS output.
Page 7
Left and Right channel D to A stages
The Wolfson WM8740 stereo DAC requires +5V(A)
and a +3V3 supply along with the Digital Audio data
lines already described in this guide.
The Left channel output only will be described in this
section as all audio output stages are the identical (all
six channels of a DV79) apart from the HDCD gain
switching for L + R only.
IC400B
Bessel filter with a differential input and a gain of 1 this
follow by a output buffer
control by the switching chip at location IC402, in
normal use the Gain of IC401B is set to 1.1 but in
HDCD
in parele with R413 and the gain is set to 2.2 allowing
for the higher audio output required by the HDCD
standard.
C436 is a A.C coupling capacitor used to remove the
few mV of offset that the DAC produces, D400
provides protection against from ESD.
The all
V chip but will also mute the outputs instantly under
mains failure conditions. Switching drive is provided
by TR401 (MUTE_BUF) and TR400 (AC_PRES) the
relays are in mute mode if either the input to TR401 is
Low or if the input to TR400 is high.
Please note:
outputs of the left/right audio stages.
Video Encoder
The video encoder at location
devices ADV7310 video encoder, supporting
interlaced and progressive scan video. Please note
the 0.1% tolerance components around this stage.
IC703 runs on a 2.5V supply provided by
voltage reference for the chip of 1.225V is provided by
REF700
R736 form an external PLL filter.
The Data lines into the encoder arrive as VIDP0 – 19
from the outputs of the VADDIS V chip.
The external current setting resistors for the internal
DACS are seen as R721-R722 and R738-R739 these
set the correct output level for the DACS.
The encoder gives out
S-Video (Y and C) and shared YUV/RGB signals. The
setting of the RGB or YUV mode is select with the
Video settings page of the Setup menu.
and associated components for a 2nd order
IC401B
The
IC402
switches a second 10k resistor
are under control of the Vaddis
Scart
left/right audio is fed from the
6 video signals
mode the
output relays
and should be seen on
, the gain of IC401B is
IC703
is an Analogue
REG700
Pin 46
. C730-731 and
, for composite,
the
six analogue output
The
o DAC_A = Composite
o DAC_B = SVID Y
DAC_C = SVID C
o
o DAC_D = Y or Green
o DAC_E = U or Blue
o DAC_F = V or Red
Please note: When the player is in Progressive scan
mode the composite and S-Video signals will be
switched off.
The Video outputs from IC703 are filtered by six identical
filters. For instance if we look at the Composite stage we
will see a very slow roll off filter comprising of C719,
C721 with L701 and L703 the
stage is around 40Mhz, resistors R700 and R702 form a
load for the current output DAC and as such set the
relative output level.
The outputs are driven by the Video op-amp at location
IC700A
75ohm resistor,
These signals now travel to the COMMS and Video
extension card on Con 901.
SCART Output
RGB and Composite video signals as well as left and
right audio signals are all present on the SCART output
socket. As the RGB and YUV signals share the same
output port at the Vaddis V the player must be set to
RGB SCART
SCART.
RGB does not contain a Sync signal and the sync must
be taken from the Composite out (4 wire RGB).
Also present at the Scart are a number of control flags
for the monitor these include 2 GPIO control lines direct
from the Vaddis.
o ENABLE_AV
o
These are seen at the SCART output pins as.
o
o RGB STAT
The 0/6/12 line (SCART pin 8) is used to inform the
monitor of the screen format being sent by the player as
set in the video set-up section of the software.
o Standby = 0V
o
o 4:3 aspect ration = 12V
The RGB status line (SCART pin 16) will be seen as 0v
= no RGB and >1v is RGB present.
this has a gain of
D701
operation to have a RGB output on the
Please note
16/9
O/6/12
16:9 aspect ratio = 6V
signals are seen as.
–3dB
point of the filter
2.15
and is terminated by a
forms protection against ESD.
: When in RGB SCART mode the
Page 8
HDMI output stage
Please note: Due to the plug and play nature of the
HDMI/DVI interface, if presented with a reported no
HDMI problem it is worth checking all set-up
parameters of both the DVD player and the
Plasma/Projector in use before performing component
level diagnostics on this section.
HDMI is a system that transmits uncompressed digital
video and digital audio over a high speed encrypted
interface.
IC1102
SII9030 HDMI transmitter
is an
IC in essence
the chip takes the Digital Video and Audio information
and sends the Data out in HDMI format.
REG1100
is used to generate a clean regulated 3V3
power supply to Pins 18 and 33 of the HDMI chip.
IC1100 –IC1101 are 3 state octal/line drivers these
form a multiplex that switches between the 2 groups of
signals for the video data input stage of the SII9190
the multiplexer is control by the Signal from the Vaddis
V labelled as PROG/INT this will sit at logic 1 for
Progressive scan and logic 0 for interlaced.
interlaced mode
In
VIDP7-0
are passed to input port pins
the 8 bit Y/Cb/Cr video data on
D15 – D8
of the
SII9190.
Progressive scan mode
In
all 20 bits of the Video
data bus are used and get mapped as follow.
VIDP 19 -12 provide 8 msbits of Y data to pins D15-8
VIDP 11 -10 provide 2Isbits of Y data to pins D2-3
VIDP 9 - 2 provide 8 msbits of Cb/Cr data to pins D23 – 16
VIDP 1 – 0 provide 2 Isbits of Cb/Cr data to pins D7 - 6
Along with the VIDP video data lines we must also see
VSYNC – Vertical sync data
HSYNC – Horizontal sync
CLK27M_VID – 27Mhz video clock.
SPDIF – Digital audio data (Full surround)
MCLK_HDMI – Used to strobe HDMI dig audio
output
At the
of the HDMI chip we will see the
following signals at SKT100.
TMDS (Transistion Minimised Differential Signalling) this
consists of a clock signal (TXC+/TXC-) and 3 data
signals
(TX0+/TX0-, TX1+/TX1- and TX2+/TX2-).
All signals are differential and use current switching
techniques therefore no signals will be observed unless
the output is correctly terminated. In this application the
clock signal will always be 27MHz and the data signals
will be clock X10 so 270Mbit/s.
DDC Channel
this is a 12C interface on DDC_SCL and
DDC_SDA. These signals connect to the VADDIS V
which is the I2C bus master, The DDC channel is used
to read back information from the HDMI sync regarding
it’s Video and Audio capabilities and is also used for
HDCP encryption authentication.
+5V Power, the HDMI interface requires a 5V supply
capable of delivering around 50mA, the supply is
provided by REG 1101 which delivers the required
current and will shut down in the event of a short circuit.
Hotplug.
The HDMI `Hot plug’ signal HDPIN is a +5V to
signal the presence of equipment being connected, this
converted to 3v3 logic 1 as IC1100 is not +5V tolerant.
CEC.
The CEC (Consumer Electronics Control) signal is
a 1-wire bidirectional control signal. It connects to the
Vaddis via an ESD protection circuit D1102 at the
moment this line is not used at present and is an
optional part of the HDMI specification.
Page 9
Comms and Final video output stage
The signals from the main board travel up to the
Comms board on connector
CON902
.
Video signals
The
simply travel via an A-C coupling
net before exiting the player via the RCA-phono
sockets at locations
SKT902
and
SKT903
.
RS232
The
interface is on 9 way “D” type CON900,
with IC900 providing the level translation and static
protection between the RS232 levels and the
CMOS levels required by the VADDIS V,
also supplies a
+5V
Status level when ever the unit is
3.3V
CON900
not in standby this generated from a buffered version
AV_ENABLE
of the
signal as used within the SCART
output stage (0V in standby).
We have two remote input bus’s on this board, the first
can be seen to arrive at
signal received should be a
SK901
on a 3.5mm mono jack
36Khz
modulated RC5
signal, the RC5 data then travels to the front panel and
is fed to IR led that is sited just behind the front panel
IR Sensor
, we use the sensor to demodulate the and
opto-isolate the signal due to the fact that the signal is
floating up from ground.
The 3.5mm socket at location
SKT900
is used to
receive un-modulated RC5 the 0V representing a
space (equivalent to no-infra-red carrier), this input is
effectively wire-Ord with the front panel IR receiver on
IRRCV
these take the form of a 5V/0V RC5 signal,
with 5V representing a mark (equivalent to a burst of
36Khz carrier on infrared) and 0V representing a mark
(space), the signal is simply inverted and wire-ord to
the display board Infra-red led via
TR900
.
Page 10
SW2A
DGND
SDDFC30400
SW1
18-000-0019
SW2B
SDDFC30400
C49
22N
100V
MKS2
5V_NFB
3V3_NFB
R7
6K8
0W25
MF
R4
4K7 0W25
MF
C15
100N
100V
MKS2
FHLDR1
20mm HLDR
FS1 T315mA
S504
FHLDR2
20mm HLDR
FS2
T315mA
S504
CON1
3
2
1
MOLEX
44472
(NFB From PSU Outputs)
C50
22N 100V
MKS2
R10
1K0 0W25
MF
TR4
BC546B
TO-92
VN35V6
2A22B
115V230V
1A11B
MAINS SUPPLY
FOR EXT. AUDIO
SUPPLY TX
R11
9K1
0W25
MF
TR8
BC556B
TO-92
VN35V6
R26
68R
0W25
MF
R27
2K7
0W25
MF
USED TO SECURE TRANSFORMER CABLES TO PCB NEAR CON1
6
5
4
C51
22N
100V
MKS2
C16
100N
100V
MKS2
GREY
BLACK
3
4
GREY
DK GREY
CON2
WAGO
256
NOTE TRANSFORMER TX1 IS MOUNTED ON
THE CHASSIS AND CONNECTED TO THE PSU
PCB BY CON2,3,4. TX1 IS SHOWN ABOVE FOR
CIRCUIT OPERATION
DGND
R12
10K
0W25
MF
R14
NF
R15
10K
0W25
MF
C56
4N7
100V
CER
R28
22R
0W25
MF
SKT1
BULGIN
PX0580
SH1
NF
EMC Shield
N
E
L
QTYDESCRIPTIONPART No.NOTESITEM
R9
1K0 0W25
MF
PSU_CLK
ITEM11Clip For SW Profile HeatsinkF006
ITEM21Sil Pad For TO-220 HS InsulatorF082
ITEM32Fuseholder Cover For 20mm FuseholderF022
ITEM41Blank PCB DV78 PSUL959PB
ITEM61Cable Tie 100MM X 2.5MMF044
ITEM51Earth Lead Assy 75MM8M101SAFETY EARTH WIRE FROM IEC INLET SK1 TO METAL CHASSIS
ITEM72Rivet CopperHP007SRIVETS TO SECURE IEC INLET TO PCB
C1C3
NF
4
1
C2
NF
VP5V
C47
22P
100V
N150
DGND
DGND
R8
1K0
0W25
MF
TR3
BC546B
TO-92
R13
10K
0W25
MF
TR7
BC556B
TO-92
R25
100R
0W25
MF
3N3
250V
3
CER
L1
250U
2
C4
3N3
250V
CER
C14
100N
100V
MKS2
VN35V6
C48
1N0
100V
CER
WHITE
BLUE
2
1
LT GREY
DZ6
BZX79C
12V
DO-35
BLUE
1
115V
2
3
115V
4
C17
100N
100V
MKS2
VN35V6VN35V6VN35V6
2
VFB
1
COMP
8
VREF
4
RT/CT
R29
82K 0W25
MF
TX1
Small Toroidal Mains
L924TX
7
1
GREEN
CON3
WAGO
256
7
VCC
GND
5
FIX1
Dia 3.5mm
FIX2
Dia 3.5mm
5
6
TR5
BD179
TO-126
R17
10R
0W25
MF
OUT
ISEN
1
GREY2GREY
CON4
WAGO
256
VN35V6
1
1
C40
220UF
16V
YXF
IC1
UC3843AN
DIP-8
6
3
VN35V6
C5
NF
33R 0W25
C52
330P
100V
N750
R24
MF
R16
47K
0W25
MF
FIX3
Dia 3.5mm
FIX4
Dia 3.5mm
HS1B
SW38-2
10.2C/W
R5
4K7 0W25
MF
1
1
D1
2KBP02
DGND
M1
IRF640N
TO-220
R30
0R22
3W
SPRX
FIX5
Dia 3.5mm
FIX6
Dia 3.5mm
C6
100N
100V
MKS2
1
1
C27
1000UF
63V
YK
L2
NF
LK1
0R0 0W 25 MF
C7
100N
100V
MKS2
TX2
Ferrite Switch Mode
L925TX
C36
1N0
100V
CER
R31
10R
0W25
MF
C28
1000UF
63V
YK
111
16T
2
16T
3
SCR
DGND
FD1
FD2
41T
41T
22T
14T
10T
VN35V6
4
5
6
12
9
10
7
8
TOOL1
TOOL2
TOOL3
TOOL4
C8
100N
100V
MKS2
C32
470pF
1kV
DE
R20
470R
0W25
MF
1N0 100V
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
When updating the design, modify this schematic first.
The PCB is updated from this schematic.
Also update the DV79 schematic and DV75 schematic,
and get the DV79 and DV75 BOMs from their own
schematics
ATE can use test pad to put in debug boot mode
Fit Link to boot from DEBUG UART
R236
4K7
0W125
0805
P278
R221
0R0
0W125
0805
+3V3D
C241
1N0
50V
0603
DGND
+1V8D
C242
1N0
50V
0603
DGND
27
RP215A
RP215B
4K7
4K7
62mW
62mW
1206
1206
R230
1K0
0W125
0805
CON200
1
2
HARWIN
M20-973
R229
1K0
0W125
0805
Decoupling caps on bottom of board
C243
1N0
50V
0603
Decoupling caps on bottom of board
C244
1N0
50V
0603
To enable Vaddis PLL for testing:
Make PLLCFGA low
Isolate AMCLK from GCLKA
Link GCLKA to GCLKP
Connect AMCLK_OUT to AMCLK
AMCLK is now an output and the Vaddis PLL is
enabled
DRAWING TITLE
DRAWING TITLE
A & R Cambridge Ltd.
A & R Cambridge Ltd.
Pembroke Avenue
Pembroke Avenue
Waterbeach
Waterbeach
Cambridge CB5 9QR
DV29 MAIN VADDIS V
DV29 MAIN VADDIS V
Filename:
L971C2.sch
Filename:
L971C2.sch
Notes:
Notes:
ECO No.DESCRIPTION OF CHANGE
Contact Engineer:
Contact Engineer:24-Aug-2004
Contact Tel: (01223) 203270Peter Gaggs
Contact Tel: (01223) 203270Peter Gaggs
ECO No.DESCRIPTION OF CHANGE
PG1.004_E12109-08-04 Production release
DATE
INITIALS
DATE
INITIALS
24-Aug-2004
Printed:
Printed:
211Sheetof
211Sheetof
A1
DRAWING NO.
L971C2
ISSUE
ISSUE
Page 15
others 1 1 OFF
C302
100N
16V
0603
REG300
LM1086CS-3.3
TO-263
FSEL0
X300
27MHz
HC49
+3V3
P302
C342
100N
16V
0603
7
8
14
16
+3V3PLL
C303
100UF
10V
YXF
XTI
XTO
FSEL
NC
+5VD
DGNDDGND
C300
27P
100V
0805
C301
DGND
27P
100V
0805
CLOCK GENERATOR
C306
100N
16V
0603
DGND
5
VDD2
MO1
MO2
AO1
AO2
SO1
SO2
VSS2
6
1
2
VDD312VDD1
IC300
SM8707E
VSOP-16
VSS311VSS1
C311
100N
16V
0603
3
4
9
10
13
15
C308
100N
16V
0603
R300
75R 0603
P341
R301
P340
100R 0603
P342
R306
100R
0603
P343
P344
FSEL1
ENABLE_AV
P345
27MHz
CLK27M_VADDIS
P346
CLOCK DIVIDER
+3V3D
12
D
11
CLK
1
4
2
IC303A
SN74AHC1G00DBVR
DBV-5
P356
10
IC306B
9
P349
Q
SD
P348
R323
8
Q
RD
13
100R 0603
74LVC74AD
S0-14
P347
Ensures audio clock can be trurned off in standby mode
R308
100R 0603
P357
98
1211
AUDIO CLOCK BUFFER
IC301A
1
OE
DGND
2
A0
4
A1
6
P360
A2
8
A3
74LVC244APW
TSSOP-20
IC301B
19
OE
17
A0
15
A1
13
A2
11
A3
74LVC244APW
DGND
TSSOP-20
Spare clock buffer used to buffer mute control
P358
P359
P350
R309
47R 0603
R322
47R 0603
MUTE*MUTE_BUF*
IC307C
10
74LVC125AD
SO-14
IC307D
74LVC125ADSO-14
13
18
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
P318
16
P319
14
P320
12
3
5
7
9
P323
P300
P321
R302
75R 0603
R303
75R 0603
R304
75R 0603
R305
1K8 0603
R310
75R 0603
R307
75R 0603
P325
P326
P327
Base resistor for TR401 here to reduce noise on MUTE_BUF*
P301
P329
PSU CLOCK DIVIDER
MCLK_DAC0
MCLK_DAC1
MCLK_DAC2
MCLK_VADDIS
MCLK_HDMI
Audio master clock frequency for different sample
rates
Fs Master clock frequency
FSEL1..0
44.1kHz 11.2896MHz (256 x Fs) 00
48kHz 12.288MHz (256 x Fs) 01
88.2kHz 22.5792MHz (256 x Fs) 10
96kHz 24.576MHz (256 x Fs) 11
176.4kHz 22.5792MHz (128 x Fs) 10
192kHz 24.576MHz (128 x Fs) 11
DGND
2
D
3
CLK
23
4
SD
RD
74LVC74AD
1
S0-14
IC307A
1
74LVC125AD
SO-14
ALRCLK
ABCLK
IC306A
5
Q
6
Q
DGND
ADAT0
ADAT1
ADAT2
56
P334
P335
IC307B
4
74LVC125AD
SO-14
P361
P364
P365
+3V3D
DGND
DGND
DGND
C305
100UF
10V
YXF
DGND
DGND
DGND
I2S BUFFER
IC302A
1
OE
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC302B
19
OE
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
IC309A
1
OE
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC309B
19
OE
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
IC307E
VCC
C307
100UF
10V
GND
YXF
74LVC125AD
SO-14
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
+3V3D
DGND
14
7
P352
+3V3D
P353
IC304A
5
6
R319
1K0
0W125
0805
ITEM3001Pad Damping 7.5x6x3MM RubberE828APFit on one side of X300 (see assembly drawing)
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
10
D
CLK
+3V3D
DGND
C321
47P
100V
0805
NF
13
IC304B
Q
SD
Q
RD
74LVC74AD
S0-14
P362
P363
D300
BAT54S
SOT-23
9
8
P354
PSUFS0
PSUFS1
12
11
+3V3D
DV29 MAIN CLOCKS & SPDIF
Filename:
L971C3.Sch
Notes:
Contact Engineer:
DGND
C343
100N 50V
0805
DV29
IC305A
4
I0
3
I1
2
I2
1
I3
15
I4
14
I5
13
I6
12
I7
11
S0
10
S1
9
S2
7
E
74HC151D
SO-16
DV79, DV75
DGND
C315
100N50V0805
Contact Tel: (01223) 203270Peter Gaggs
5
P355
Y
6
Y
TX301
PCB Mount SMT
7A29398
R311
100R 0603
51
84
NF
DGND
ECO No.DESCRIPTION OF CHANGE
PSUCLK
P304
2
3
P336
C316
R320
100N
50V
0805
INITIALS
Printed:
NF
0R0
0W125
0805
PG1.004_E12109-08-04 Production release
DATE
24-Aug-2004
PSUCLK SHOULD BE 44.1kHz OR 48kHz
Fs PSUFS1 PSUFS0 PSUCLK
44.1kHz 0 0 44.1kHz
48kHz 0 0 48kHz
88.2kHz 0 1 44.1kHz
96kHz 0 1 48kHz
176.4kHz 1 0 44.1kHz
192kHz 1 0 48kHz
1
L301
1000R @ 100MHz
4
DLW31S
311Sheetof
C322
100P
100V
0805
NF
SPDIF_OUT
SPDIF_GND
C323
10N
50V
0603
A2
SKT300
KUNMING
GOLD
EMC_GND
DRAWING NO.
SCRN
ISSUE
L971C3
R315
750R 0603
R316
750R 0603
R317
750R 0603
IC306C
C320
100N
16V
0603
74LVC74AD
S0-14
VCC
GND
P351
2
3
+3V3D
D
CLK
14
7
+3V3D
4
1
DGND
Q
SD
Q
RD
74LVC74AD
S0-14
PSUFS0
PSUFS1
R318
120R
0W125
0805
C324
100N
16V
0603
RP301A
P311
18
100R 1206
RP301B
P366
C317
100N
16V
0603
P312
P313
P305
P306
P368
P307
P371
27
100R 1206
RP301C
100R 1206
RP300A
18
100R 1206
RP300B
27
100R 1206
RP300C
100R 1206
R313
56R
0W125 0805
RP302A
18
100R 1206
RP302C
100R 1206
R312
100R 0603
C326
100N
16V
0603
IC301C
VCC
GND
74LVC244APW
TSSOP-20
18
16
14
12
3
5
7
9
18
16
14
12
3
5
7
9
C325
100N
16V
0603
P314
P315
P316
63
P308
P309
P310
63
P317P303
P372
63
P374
P376
C327
C328
100N
100N
16V
16V
0603
0603
20
C309
100N
16V
10
0603
C329
100N
16V
0603
IC302C
20
VCC
10
GND
74LVC244APW
TSSOP-20
ALRCLK_DAC0
ALRCLK_DAC1
ALRCLK_DAC2
ABCLK_DAC0
ABCLK_DAC1
ABCLK_DAC2
ABCLK_HDMI
ADAT_DAC0
ADAT_DAC1
ADAT_DAC2
C330
100N
16V
0603
C310
100N
16V
0603
C331
100N
16V
0603
IC309C
20
VCC
10
GND
74LVC244APW
TSSOP-20
C332
100N
16V
0603
C318
100N
16V
0603
C333
100N
16V
0603
SPDIF
C334
100N
16V
0603
IC304C
VCC
GND
74LVC74AD
S0-14
SPDIF COAX OUTPUT
IC308B
56
4
DGND
5
3
C339
100N
16V
0603
IC308C
98
10
IC308D
1211
13
DGND
C304
100UF
10V
YXF
C319
100N
16V
0603
P324
14
7
IC308A
23
74LVC125AD
1
SO-14
DGNDDGND
SPDIF_OP
+5VD
2
VCC
1
I/P
GND
3
DGND
C335
C336
100N
100N
16V
16V
0603
0603
IC305B
16
VCC
C312
100N
16V
0603
GND
74HC151D
SO-16
8
R314
P328P330
100R 0603
R321
75R 0603
OPTICAL OUT
TX300
JFJ1001-010010
C337
C338
100N
100N
16V
16V
0603
0603
VCC
C313
100N
16V
GND
0603
IC303B
SN74AHC1G00DBVR
DBV-5
C314
100N
50V
0805
P322
74LVC125AD
SO-14
P331
74LVC125AD
SO-14
P332P333P337
74LVC125AD
SO-14
C340
C341
100N
100N
16V
16V
0603
0603
IC308E
14
VCC
7
GND
74LVC125AD
SO-14
Page 16
Audio outputs are inverted so as to be compatible with
DV88. This is compenstaed for in software by setting a
register in the DAC to invert the signal
+5VA
C400
10UF
35V
SGET
DGND
+3V3A
L400
120R@100MHz
ALRCLK_DAC0
ADAT_DAC0
ABCLK_DAC0
MCLK_DAC0
MD
MC
ML_8740_0
RESET*
+12VA
+5VA
C421
100N
50V
C423
0805
100N
50V
0805
-12VA
C422
100N
50V
0805
DGND
C406
100N
50V
0805
DGND
ALRCLK_DAC0
ADAT_DAC0
ABCLK_DAC0
MCLK_DAC0
MD
MC
ML_8740_0
RESET*
IC402E
13
V+
12
VL
5
GND
4
V-
DG413DY
SO-16
C407
100N
50V
0805
C402
10UF
35V
SGET
+3V3_DAC0
P400
P401
P438
P402
C408
100N
50V
0805
+3V3_DAC0
C414
100N
50V
0805
DGND
1
LRCKIN
2
DIN
3
BCKIN
5
SCLK
26
MD/DM0
27
MC/DM1
28
ML/I2S
23
CSBIOW
24
MODE
4
MODE8X
6
DIFFHW
25
MUTEB
22
RSTB
IC402C
DG413DY
SO-16
9
8
7
DGND
DVDD
DGND
1011
DAC
15
20
AVDD
AVDDL
AGNDL
AGND
14
19
+3V3_DAC0
DGND
9
AVDDR
VOUTL+
VOUTL-
VOUTR+
VOUTR-
VMIDL
VMIDR
ZERO
AGNDR
XWM8740EDS
10
SSOP-28
R416
10K
0W125
0805
NF
IC402D
DG413DY
SO-16
16
IC403
17
16
12
13
18
11
C403
10UF
21
35V
SGET
DGND
CON400
1
2
HARWIN
M20-973
DGND
NF
Useful for drop-out test
1415
P408
P409
C415
100N
50V
0805
P415
P416
C424
47P
100V
0805
C412
100N
100V
MKS2
C425
47P
100V
0805
R400
3K3
0W125
0805
R401
3K3
0W125
0805
C404
10UF
35V
SGET
R404
3K3
0W125
0805
R405
3K3
0W125
0805
FILTER
2nd order Bessel filter, Av=1
C426
R402
2N2
3K3
100V
0W125
FKP2
0805
DGND
C427
2N2
100V
FKP2
DGND
C416
C413
100N
100N
50V
100V
0805
MKS2
2nd order Bessel filter, Av=1
P417
C428
R406
2N2
3K3
100V
0W125
FKP2
0805
DGND
C429
2N2
100V
FKP2
DGND
R408
680R
0W125
0805
R410
680R
0W125
0805
DGND
R409
680R
0W125
0805
+12VA
DGND
R411
680R
0W125
0805
-12VA
C430
680P
100V
FKP2
C432
680P
100V
FKP2
C401
10UF
35V
SGET
C405
10UF
35V
SGET
5
6
C431
680P
100V
FKP2
R403
3K3
0W125
0805
GAIN_SCALING
1=HDCD gain, 0=normal
C409
100N
50V
0805
3
2
C433
680P
100V
FKP2
R407
3K3
0W125
0805
C417
100N
50V
0805
84
IC400B
7
OPA2134UA
SO-8
AC_PRES*
IC400A
1
OPA2134UA
SO-8
MUTE_BUF*
P421
P414
GAIN_SCALING
MUTING
MUTE_BUF*
AC_PRES*
Base resistor on PSU
R413
10K
0W125
0805
IC402B
DG413DY
P422
P428
SO-16
P431
P436
DGND
23
IC402A
DG413DY
SO-16
R418
10K
0W125
0805
R412
10K
0W125
0805
Base resistor on sheet 3
P435
R417
10K
0W125
0805
8
DGND
+5VD
TR400
BC849B
SOT-23
1
R415
10K
0W125
0805
D404
BAS16
SOT-323
DGND
OUTPUT BUFFER
Gain of -2.2 for HDCD, otherwise -1.1
Cheapo version could have bipolar op-amp, but without feedback round coupling cap
IC401B
6
5
OPA2134UA
SO-8
RLY500C
NEC
EB2-5NU
R436
100R
0W125
0805
C441
1N0
100V
0805
C442
1N0
100V
0805
C443
DGNDEMC_GND
1N0
100V
0805
C410
100N
50V
0805
IC401A
84
2
3
OPA2134UA
SO-8
C411
100N
50V
0805
67
P437
TR401
FMMT497
SOT-23
P429
P423
RLY400C
NEC
EB2-5NU
DGND
+12VA
DGND
DGND
DGND
-12VA
R420
11K
0W125
0805
C434
33P
100V
0805
P424P427
7
RLY600C
NEC
EB2-5NU
D401
BAT54S
SOT-23
R421
11K
0W125
0805
C435
33P
100V
0805
P430
1
R422
1M0
0W125
0805
R423
1M0
0W125
0805
R424
47R
0W125
0805
R426
47R
0W125
0805
DGND
DGND
C436
100UF
16V
NONP
C437
100UF
16V
NONP
+12VA
D400
BAT54S
SOT-23
-12VA
DGND
R414
47K
0W125
0805
RLY400A
NEC
EB2-5NU
R425
47R
0W125
0805
R434
1K0
0W125
0805
R428
0R0 0W 125
0805
LEFT_OUT
SCART_LEFT
LEFT
SKT400
KUNMING GOLD
OUT_GND1OUT_GND2
C444
1N0
100V
0805
C439
100P
100V
0805
C438
C418
100P
100P
100V
100V
0805
+12VA
-12VA
0805
D403
BAT54S
SOT-23
R430
0R0 0W 125
0805
R429
0R0
DGNDDGND
0805
P434
R427
47R
0W125
0805
R419
47K
0W125
0805
DGND
RLY400B
NEC
EB2-5NU
R435
1K0
0W125
0805
C440
1N0
100V
0805
SCRN
EMC_GND
RIGHT_OUT
SCART_RIGHT
C419
100P
100V
0805
R431
0R0
0805
RIGHT
ITEM4001Pad Damping 7.5x6x3MM RubberE828AP
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
DV29 MAIN DAC L & R AUDIO
Filename:
Notes:
Contact Engineer:
L971C4.Sch
Fit on top of RLY400
PG1.004_E12109-08-04 Production release
INITIALS
Printed:
DATE
24-Aug-2004
411Sheetof
A2
DRAWING NO.
Contact Tel: (01223) 203270Peter Gaggs
ECO No.DESCRIPTION OF CHANGE
ISSUE
L971C4
Page 17
ALRCLK_DAC1
ADAT_DAC1
ABCLK_DAC1
MCLK_DAC1
MD
MC
ML_8740_1
RESET*
Audio outputs are inverted so as to be compatible with
DV88. This is compenstaed for in software by setting a
register in the DAC to invert the signal
+5VA
C500
C506
100N
50V
0805
DGND
C507
100N
50V
0805
C502
10UF
35V
SGET
+3V3_DAC1
P531
10UF
35V
SGET
DGND
+3V3A
120R@100MHz
L500
ALRCLK_DAC1
ADAT_DAC1
ABCLK_DAC1
MCLK_DAC1
MD
MC
ML_8740_1
RESET*
C508
100N
50V
0805
+3V3_DAC1
C514
100N
50V
0805
DGND
26
27
28
23
24
25
22
1
2
3
5
4
6
LRCKIN
DIN
BCKIN
SCLK
MD/DM0
MC/DM1
ML/I2S
CSBIOW
MODE
MODE8X
DIFFHW
MUTEB
RSTB
DGND
P518
C535
470P
100V
0805
+12VA
D500
BAT54S
SOT-23
-12VA
R524
0R0
0805
SKT500
KUNMING GOLD
C536
1N0
100V
0805
EMC_GND
LS_OUT
LEFT SURR
RIGHT SURR
C519
470P 100V
C518
0805
470P
100V
C537
1N0
100V
0805
0805
OUT_GND3OUT_GND4
SCRN
0R0
0805
R527
ALL PARTS ON THIS SHEET ARE NOT FITTED FOR DV75
FILTER
2nd order Bessel filter, Av=1
C522
R502
2N2
3K3
100V
0W125
FKP2
0805
DGND
C523
2N2
100V
FKP2
DGND
C516
C513
100N
100N
50V
100V
0805
MKS2
R508
680R
0W125
0805
R509
680R
0W125
0805
C526
680P
100V
FKP2
C527
680P
100V
FKP2
R503
3K3
0W125
0805
IC500B
5
7
6
OPA2134UA
SO-8
P513P514
R512
10K
0W125
0805
C520
47P
100V
0805
R500
3K3
0W125
0805
R501
3K3
0W125
0805
P507
P508
DAC
8
15
9
20
DVDD
AVDD
AVDDL
DGND
AGNDL
AGND
7
14
19
10
AVDDR
AGNDR
VOUTL+
VOUTL-
VOUTR+
VOUTR-
VMIDL
VMIDR
ZERO
IC502
17
16
12
13
18
11
21
DGND
XWM8740EDS
SSOP-28
C503
10UF
35V
SGET
C515
100N
50V
0805
C512
100N
100V
MKS2
C504
10UF
35V
SGET
OUTPUT BUFFER
Gain of -1.1
Cheapo version could have bipolar op-amp, but without feedback round coupling cap
IC501B
6
5
DGND
OPA2134UA
SO-8
R516
11K
0W125
0805
R518
C530
1M0
33P
0W125
100V
0805
0805
P515
7
R520
47R
0W125
0805
DGND
C532
100UF
16V
NONP
CENTRE
CENTRE_OUT
From sheet 6
SUB_OUT
SUB
R525
0R0
DGNDDGND
0805
DGND
R521
47R
0W125
0805
R513
47K
0W125
0805
RLY500B
NEC
EB2-5NU
CENTRE_OUT
SUB_OUT
C534
470P
100V0805
P520
P519
C521
47P
100V
0805
R504
3K3
0W125
0805
R505
3K3
0W125
0805
2nd order Bessel filter, Av=1
P521
C524
R506
2N2
3K3
100V
0W125
FKP2
0805
DGND
C525
2N2
100V
FKP2
DGND
R510
680R
0W125
0805
DGND
+12VA
DGND
R511
680R
0W125
0805
-12VA
C528
680P
100V
FKP2
C501
10UF
35V
SGET
C505
10UF
35V
SGET
C509
100N
50V
0805
C529
680P
100V
FKP2
R507
3K3
0W125
0805
C517
100N
50V
0805
+12VA
-12VA
24-Aug-2004
D501
BAT54S
SOT-23
R526
0R0 0W 125
0805
Fit on top of RLY500
DATE
511Sheetof
RS_OUT
A2
DRAWING NO.
ISSUE
L971C5
R517
+12VA
C510
100N
50V
0805
IC500A
84
3
1
2
OPA2134UA
SO-8
P525P526
R514
10K
0W125
0805
DGND
DGND
DGND
-12VA
ITEM5001Pad Damping 7.5x6x3MM RubberE828AP
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
IC501A
84
2
3
OPA2134UA
SO-8
C511
100N
50V
0805
DV29 MAIN DAC LS & RS AUDIO
Filename:
Notes:
Contact Engineer:
11K
0W125
0805
R519
C531
1M0
33P
0W125
100V
0805
0805
1
P527
L971C5.Sch
R522
47R
0W125
0805
C533
100UF
16V
NONP
R515
47K
0W125
0805
DGND
RLY500A
DGND
NEC
EB2-5NU
Contact Tel: (01223) 203270Peter Gaggs
P530
R523
47R
0W125
0805
PG1.004_E12109-08-04 Production release
ECO No.DESCRIPTION OF CHANGE
INITIALS
Printed:
Page 18
Audio outputs are inverted so as to be compatible with
DV88. This is compenstaed for in software by setting a
register in the DAC to invert the signal
+5VA
C600
C606
10UF
100N
35V
50V
SGET
0805
DGND
+3V3A
L600
DGND
ALRCLK_DAC2
ADAT_DAC2
ABCLK_DAC2
MCLK_DAC2
MD
MC
ML_8740_2
RESET*
C602
10UF
35V
SGET
+3V3_DAC2
ALRCLK_DAC2
ADAT_DAC2
ABCLK_DAC2
MCLK_DAC2
MD
MC
ML_8740_2
RESET*
120R@100MHz
C607
100N
50V
0805
P631
C608
100N
50V
0805
+3V3_DAC2
C614
100N
50V
0805
DGND
26
27
28
23
24
25
22
1
2
3
5
4
6
LRCKIN
DIN
BCKIN
SCLK
MD/DM0
MC/DM1
ML/I2S
CSBIOW
MODE
MODE8X
DIFFHW
MUTEB
RSTB
DGND
P618
+12VA
-12VA
D600
BAT54S
SOT-23
R624
0R0 0W 125
0805
Connector on sheet 5
CENTRE_OUT
OUTPUT BUFFER
ALL PARTS ON THIS SHEET ARE NOT FITTED FOR DV75
FILTER
2nd order Bessel filter, Av=1
C622
R602
2N2
3K3
100V
0W125
FKP2
0805
DGND
C623
2N2
100V
FKP2
DGND
C616
C613
100N
100N
50V
100V
0805
MKS2
R608
680R
0W125
0805
R609
680R
0W125
0805
C626
680P
100V
FKP2
C627
680P
100V
FKP2
R603
3K3
0W125
0805
IC600B
5
7
6
OPA2134UA
SO-8
P613P614
R612
10K
0W125
0805
C620
47P
100V
0805
R600
3K3
0W125
0805
R601
3K3
0W125
0805
P607
P608
DAC
8
15
9
20
DVDD
AVDD
AVDDL
DGND
AGNDL
AGND
7
14
19
10
AVDDR
AGNDR
VOUTL+
VOUTL-
VOUTR+
VOUTR-
VMIDL
VMIDR
ZERO
IC602
17
16
12
13
18
11
21
DGND
XWM8740EDS
SSOP-28
C603
10UF
35V
SGET
C615
100N
50V
0805
C612
100N
100V
MKS2
C604
10UF
35V
SGET
Gain of -1.1
Cheapo version could have bipolar op-amp, but without feedback round coupling cap
IC601B
6
5
DGND
OPA2134UA
SO-8
R616
11K
0W125
0805
R618
C630
1M0
33P
0W125
100V
0805
0805
P615
7
R620
47R
0W125
0805
DGND
C632
100UF
16V
NONP
DGND
R613
47K
0W125
0805
RLY600B
NEC
EB2-5NU
R621
47R
0W125
0805
P620
P619
C621
47P
100V
0805
R604
3K3
0W125
0805
R605
3K3
0W125
0805
2nd order Bessel filter, Av=1
C624
R606
2N2
3K3
100V
0W125
FKP2
0805
DGND
C625
2N2
100V
FKP2
DGND
R610
680R
0W125
0805
DGND
+12VA
DGND
R611
680R
0W125
0805
-12VA
C628
680P
100V
FKP2
C601
10UF
35V
SGET
C605
10UF
35V
SGET
C609
100N
50V
0805
C629
680P
100V
FKP2
R607
3K3
0W125
0805
C617
100N
50V
0805
+12VA
-12VA
24-Aug-2004
D601
BAT54S
SOT-23
R626
0R0 0W 125
0805
Fit on top of RLY600
DATE
Connector on sheet 5
SUB_OUT
611Sheetof
A2
DRAWING NO.
ISSUE
L971C6
R617
+12VA
C610
100N
50V
0805
IC600A
84
3
1
2
OPA2134UA
SO-8
P625P626
R614
10K
0W125
0805
DGND
DGND
DGND
-12VA
ITEM6001Pad Damping 7.5x6x3MM RubberE828AP
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
IC601A
84
2
3
OPA2134UA
SO-8
C611
100N
50V
0805
DV29 MAIN DAC CENTRE & SUB
Filename:
Notes:
Contact Engineer:
11K
0W125
0805
R619
C631
1M0
33P
0W125
100V
0805
0805
P627
1
L971C6.Sch
R622
47R
0W125
0805
C633
100UF
16V
NONP
R615
47K
0W125
0805
DGND
RLY600A
DGND
NEC
EB2-5NU
Contact Tel: (01223) 203270Peter Gaggs
P630
R623
47R
0W125
0805
PG1.004_E12109-08-04 Production release
ECO No.DESCRIPTION OF CHANGE
INITIALS
Printed:
Page 19
AUDIO
SCART_RIGHT
SCART_LEFT
SCART control signals
ENABLE_AV: 0 in when standby mode, 1 when on
(3V3 levels)
(RGB_STAT is supposed to be >1V when driving 75R)
16/9: 0 when 4:3 output, 1 when 16:9 output (3V3
levels)
0/6/12: 0V in standby, 6V when output is 16:9, 12V
when output is 4:3
ENABLE_AV
CONTROL
16/9
+5V_VID
R801
1K0
0W125
0805
P810
P811
TR801
MMUN2211LT1
SOT-23
DGND
P812
R807
4K7
0W125
0805
R806
6K8
0W125
0805
P814
TR802
MMUN2211LT1
SOT-23
DGND
P815
P816
+12VD
+5V_VID
DGND
TR800
MMUN2111LT1
SOT-23
TR803
BC849B
SOT-23
P817P818
R808
10K
0W125
0805
TR804
BC849B
SOT-23
P819
R811
1K0
0W125
0805
R809
330R
0W125
0805
R812
82R
0W125
0805
VIDEO
R810
330R
0W125
0805
RGB_STAT
SCART_BLUE
SCART_GREEN
SCART_RED
SCART_COMPOSITE
+12VD
D800
BAT54S
SOT-23
DGND
0/6/12
+5V_VID
D801
BAT54S
SOT-23
DGND
DGND
DGND
DGND
C806
100N
50V
0805
C807
100N
50V
0805
C802
47P
100V
0805
DGND
C803
47P
100V
0805
C800
47P
100V
0805
C804
47P
100V
0805
C801
47P
100V
0805
R800
0R0
0W125
0805
C805
47P
100V
0805
SCART OUTPUT
10
11
12
13
14
15
16
17
18
19
20
21
SKT800
1
2
3
4
5
6
7
8
9
CHARM
CW
SCART_RIGHT
SCART_LEFT
SCART_AGND
SCART_BLUE
0/6/12
SCART_GREEN
SCART_RED
RGB_STAT
SCART_COMPOSITE
C811
1N0 100V 0805
C812
1N0 100V 0805
DGNDEMC_GND
C813
10N
50V
0603
R803
100R
0W125
0805
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
2. Interlaced Mode: 8 Bit multiplexed YCbCr
Vaddis V Output Function SiI9190 Input
VIDP7..0 YC7..0 D15..8
1=Prog scan, 0=Interlaced
PROG/INT*
+3V3D
C1134
C1135
C1136
100N
100N
16V
0603
100N
16V
0603
DGND
16V
0603
Around video bus
+3V3D
IC1100C
20
VCC
C1121
100UF
10V
YXF
GND
74LVC244APW
TSSOP-20
C1111
100N
16V
10
0603
DGND
PROG/INT*
+3V3D
R1114
10K
0805
DGND
C1137
100N
16V
0603
IC1101C
VCC
GND
74LVC244APW
TSSOP-20
VIDP[0..19]
TR1102
MMUN2211LT1
SOT-23
C1138
100N
16V
0603
20
10
VIDP[0..19]
P1130
P1131
C1112
100N
16V
0603
VIDP7
VIDP6
VIDP5
VIDP4
VIDP19
VIDP18
VIDP17
VIDP16
VIDP3
VIDP2
VIDP1
VIDP0
VIDP15
VIDP14
VIDP13
VIDP12
IC1103B
VCC
GND
74LV164D
S0-14
+3V3D
14
7
C1143
100N
50V
0805
IC1100A
1
OE
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC1100B
19
OE
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
IC1101A
1
OE
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC1101B
19
OE
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
C1144
100N
16V
0603
REG1102
LM1086CS-ADJ
TO-263
ADJ
P1134
18
Y0
16
Y1
14
Y2
12
Y3
3
Y0
5
Y1
7
Y2
9
Y3
18
Y0
16
Y1
14
Y2
12
Y3
3
Y0
5
Y1
7
Y2
9
Y3
IC1104B
VCC
GND
74LVC157AD
S0-16
HSYNC*
16
8
R1100
120R
0W125
0805
R1101
56R
0W125
0805
P1114
P1115
P1116
P1117
P1122
P1123
P1124
P1125
HSYNC*
CLK27M_VID
C1145
100N
16V
0603
RP1100A
RP1100B
RP1100C
RP1100D
RP1101A
RP1101B
RP1101C
RP1101D
+3V3D
+3V3D
+5VD
C1142
100UF
10V
YXF
DGND
18
27
18
27
IC1103A
1
DSA
2
DSB
8
CP
9
MR
74LV164D
S0-14
REG1100
LM1086CS-3.3
TO-263
C1100
100N
16V
0603
+3V3
DGND
+3V3D
+1V8_HDMI
Some decoupling
caps are on
bottom of PCB
9190_INT*
100R
HD15
100R
HD14
100R
63
54
63
54
HD13
100R
HD12
100R
HD11
100R
HD10
100R
HD9
100R
HD8
P1137
3
Q0
4
Q1
5
Q2
6
Q3
10
Q4
11
Q5
12
Q6
13
Q7
PROG/INT*
HSYNC DELAY CIRCUIT
delays HSYNC* by 4 clocks in
progressive mode and 8 clocks in
interlaced mode. This is to ensure
HSYNC and VSYNC falling edges
are coincident as required by HDMI
specification
70mm x 2 layers of 10mm wide double sided tape under VFD
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
DV29 DISPLAY BOARD
Filename:
L972_1.1.Sch
Notes:
Contact Engineer:
PG17-09-04 Change RX1 to KSM-902TM1N for better performance1.104_E140
PG11-08-04 Production release1.004_E123
INITIALS
Printed:
DATE
17-Sep-2004
11Sheetof
A2
DRAWING NO.
Contact Tel: (01223) 203270Peter Gaggs
ECO No.DESCRIPTION OF CHANGE
ISSUE
L972
Page 41
Page 42
DV29 DVD player Display board L972AY issue 1.1.0
DesignatorPartDescription
C12J410Capacitor SM 0805 X7R Ceramic 10% 50V 100N
C22J410Capacitor SM 0805 X7R Ceramic 10% 50V 100N
C32J410Capacitor SM 0805 X7R Ceramic 10% 50V 100N
C42J410Capacitor SM 0805 X7R Ceramic 10% 50V 100N
C52MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MM
C62MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MM
C72MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MM
C82L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C92L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C102L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C112L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C122L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C132L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C142L210Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C162MA710 Capacitor Surface Mount Electrolytic 100UF 6.3V 6.3 X 4.5MM
CON18K8616Con 1.0MM Horiz FFC 16WAY 52807 Series
CON28K2506Con CT Series Horiz 6WAY
CON38K2506Con CT Series Horiz 6WAY
D13AS16W Diode Surface Mount Small Signal BAS16W SOT-23 Package
D23AS16W Diode Surface Mount Small Signal BAS16W SOT-23 Package
D33AS16W Diode Surface Mount Small Signal BAS16W SOT-23 Package
D43AS16W Diode Surface Mount Small Signal BAS16W SOT-23 Package
DISP1B1014Display DV88
IC15H6312IC VFD Driver PT6312LQ SM LQFP-44 package
L17B822Inductor Surface Mount 2U2
LED23D013LED 5mm Red SLA-560LTT
LED33D007LED 3.1mm Green SLR-37MG3T
LED53D006LED 3mm Red/Green Tri-Colour L-93WEGW
R21M133Resistor 0805 Surface Mount 0.125W 1% 330R
R31M133Resistor 0805 Surface Mount 0.125W 1% 330R
R41M122Resistor 0805 Surface Mount 0.125W 1% 220R
R51M118Resistor 0805 Surface Mount 0.125W 1% 180R
R61M139Resistor 0805 Surface Mount 0.125W 1% 390R
R81M310Resistor 0805 Surface Mount 0.125W 1% 10K
R91M310Resistor 0805 Surface Mount 0.125W 1% 10K
R101M233Resistor 0805 Surface Mount 0.125W 1% 3K3
R111M356Resistor 0805 Surface Mount 0.125W 1% 56K
R131M310Resistor 0805 Surface Mount 0.125W 1% 10K
R141M310Resistor 0805 Surface Mount 0.125W 1% 10K
R151M310Resistor 0805 Surface Mount 0.125W 1% 10K
RX1B2109IR Receiver Module Kodenshi KSM-902TM1N
SW1A1505Switch Tact SM
SW2A1505Switch Tact SM
SW3A1505Switch Tact SM
SW4A1505Switch Tact SM
SW5A1505Switch Tact SM
SW6A1505Switch Tact SM
SW7A1505Switch Tact SM
SW8A1505Switch Tact SM
SW9A1505Switch Tact SM
TR24D10KN Digital Transistor MMUN2211LT1 SOT23 Package
TR34A849BTransistor BC849B SOT23 Package
TR44A849BTransistor BC849B SOT23 Package
TR54D10KP Digital Transistor MMUN2111LT1 SOT23 Package
Page 43
Transformer Specification for 115/230V 50/60Hz mains transformer.
Arcam Part Number L924TX
The transformer is extremely cost sensitive. It is to employ the most cost effective techniques to achieve the
specification.
The transformer output voltage will be regulated by a switch mode power supply.
The only essential specification is the fact that it must produce no acoustic noise either internally or by induced eddy
currents in steel chassis etc..
All other specifications are negotiable in the interest of allowing cost reduction. Even the use of a frame TX rather
than a toroid is negotiable providing it is silent.
330MM
TOP VIEW
1. The transformer MUST be silent when loaded to Po +10% and when supplied from Vin = 270V r.m.s.
General Safety specification.
2. To standards BS415 / EN60065 - Class I / EN60742
3. Transformer to be used in equipment which will be sold worldwide and certified to CE, CB, UL and CSA
Standards. All materials etc to be adequate for worldwide safety approvals.
6. Transformer to have dual 115V primaries to allow parallel operation for 115V input and series operation with
230V input.
7. Transformer is required to provide a mains isolation barrier and provide a single secondary winding.
8. The secondary winding is to be full wave rectified and smoothed as shown in the below diagram.
9. The DC voltage so provided will be followed by a switch mode power supply which will provide a constant power
load.
(i.e. the current drawn by the load will increase as the DC output voltage falls- hence the capacitor ripple voltage will
be higher at low input voltage)
10. The power drawn by the load has a maximum continuous rating (Po) of 22W.
11. Transformer input voltage range as follows:
115V (85V to 132.5V) windings in parallel
230V (170V to 265V) windings in series
Note. Extended input voltage range 85V to 265V
12. At minimum input voltage (170V AC) the minimum voltage on the capacitor must be > 22.5V with Po = 22W
13. At maximum input voltage and minimum load of 6W the max voltage on output capacitor must be < 63V.
14. The secondary voltages and r.m.s currents have been calculated and are tabulated against input voltage.
The model assumes the transformer regulation is made as poor as possible while meeting spec.
The equivalent series resistance of the windings transformed to the secondary is 7ohms under this condition.
Rms figures for voltages and currents are true rms figures measured with the specified bridge rectifier, Capacitor
and load resistor connected to the transformer secondary.
In the case of the load regulation for lowest cost transformer being better than the worst case specification then the
transformer voltages shall be modified so that the minimum 22.5V spec is met at 170V input and the output
voltages at 230V and 265V input voltage are lower than the specified voltages.
15. Temperature rise to be such that transformer is safe when operated in an enclosure with 50C maximum internal
temperature.
16. Toroid to be fitted with interwinding screen.
Mechanical Specification
17. Primary wires self-ended and individually sleeved for colour coding, then sleeved together.
18. Secondary wires self-ended and individually sleeved, then sleeved together.
19. Wire type used on the terminations must be such that the wire may be bent with a miniumum bend radius of
10mm through an angle of 90degrees 10times without the wire fracturing. This will allow the wires to be dressed in
production without risk of damage to terminations.
20. All wire lengths are +20, -0 mm. All wires stripped 8 +/-2mm and tinned.
21. Transformer to be marked with part number and issue number.
22. Toroidal transformer will be attached to the chassis by a dished washer and bolt (no potting required).
23. A frame transfomer meeting the above spec will be chassis mounted with flying leads and should have clamp
fitted to allow it to be screwed to chassis.
24. Toroidal transformer to be supplied with mounting kit consisting of metal dished washer and 2 neoprene or
similar washers.
Secondary Winding Voltage and Current Specs
assuming C=1360uF, f= 50Hz for Po = 22W
Bridge Rectifier Vf diode = 1.1V per leg = 2.2V Total
Ideal TX assumed with 7Ohm series resistor in secondary to simulate regulation.
AC Supply
Voltage
Pri in Series
(V r.m.s.)
170
230
265
Loaded
Secondary
Voltage
(V r.m.s.)(Ohm)(Volt)(Volt)(A r.m.s.)
23.2
37.3
44.4
AC IN
Capacitor
Peak Voltage
VpkVmin
(Volt)
26.9
46.0
55.7
Voltage on Reservoir Capacitor
Capacitor
Min Voltage
23.7
43.7
53.8
10mS
TEST CIRCUIT
Vf = 1.1V
per diode
Capacitor
Average
Voltage
25.3
44.8
54.8
+
1360uF
63V
Load Resistor
to simulate
Load RL
28
88
130
+VOUT
RL see above table.
GND
Secondary
Winding r.m.s.
Vpk
Vaverage
Vmin
Current
1.3
0.86
0.75
SECONDARY
PRIMARIES
SCREEN WIRE
GREEN/YELLOW
TX1
Small Toroidal Mains
L924TX
GREY
WHITE
PRIMARYSECONDARY
SCREEN WIRE
40mm max
BLACK
BLUE
GREEN/YELLOW
80mm dia max
1
115V
2
3
115V
4
5
RED
37.3V
6
RED
7
LEADS EXIT NEAR TOP
DRAWING TITLE
ARCAM
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
DV78 TRANSFORMER 115/230V
Filename:
Notes:
Contact Engineer:
L924TX_1.0.sch
Contact Tel: (01223) 203243Kevin Lamb
Production Release1.002-07-2003KAL03_E195
Corrected Wire Colours added notes re ClampB.021-03-2003KAL03_E086
03_E042
02_E336
ECO No.DESCRIPTION OF CHANGE
INITIALS
Printed:
DATE
7-Jul-2003
Reduced Power Output Spec, Reduced Load Regulation SpecA.14-02-2003KAL
Prototype Release
11Sheetof
A3
DRAWING NO.
A.04-12-2003KAL
ISSUE
L924TX
Page 44
NOTE.
WINDING DETAILS
TRANSFORMER IS TO BE USED ON SECONDARY SIDE OF MAINS
ISOLATION BARRIER (I.E. THIS TRANSFORMER IS NOT REQUIRED
TO PROVIDE MAINS ISOLATION BARRIER)
MAXIMUM VOLTAGE BETWEEN WINDINGS <60V
VIEW FROM SIDE OF PART
SHOWING OUTER FOIL SCREEN
SHORTED TURN FOIL SCREEN TO BE
ELECTRICALLY CONNECTED TO CORE CLAMP
CONDUCTIVE ADHESIVE FOIL MAY BE USED
FOIL TO BE COVERED IN A LAYER OF MYLAR TAPE
SEE VIEW GIVING PIN
LENGTH DIMENSIONS
ELECTRICAL REPRESENTATION
TX2
Ferrite Switch Mode
PRIMARY1
PRIMARY2
L925TX
111
16T
2
16T
3
SCR
41T
41T
22T
14T
10T
4
5
6
12
9
10
7
8
SECONDARY1
SECONDARY2
SECONDARY3
SECONDARY4
SECONDARY5
PIN 1 TO BE MARKED
VIEW FROM TOP OF PART
WITH PART INSTALLED IN PCB
1.1 INCH
NOTE PIN NUMBERING CONVENTION
ARRANGEMENT OF INTERNAL FOIL SCREENS
VIEW FROM SIDE OF PART
FOIL (2mil OR THINNER)
INSULATOR
SHOWING PIN LENGTH DIMENSIONS
BUMP FROM SCREEN JOINT TO BE
1
ADJACENT TO CORE WINDOW
TO MINIMISE LOSS OF WINDING HEIGHT
MAXIMUM OVERLAP ON ENDS OF
MATING FACE OF TX
7 REF.
PCB
2.5 MAX
2
SCREENS TO BE LESS THAN 1mm
TO MINIMISE CAPACITIVE COUPLING
WHICH WOULD PRODUCE SHORTED
TURN FOR HIGH FREQUENCY CURRENTS
SOLDER JOINTS TO BE MADE HALF WAY3
ALONG LENGTH OF FOIL FOR REDUCED LOSSES
6 to 8mm 10THOU COPPER
1
2
3
4
5
6
1.2 INCH
FULL WINDING WIDTH
SOLDER JOINT TO BE COVERED IN TAPE
JOINT MUST BE MADE TO CLEAN COPPER
(I.E. NOT THROUGH MYLAR INSULATOR)
1
2
3
4
5
6
12
11
10
9
8
7
WIRE
OUTER SCREEN
SECONDARY4
SECONDARY1 SECONDARY2
12
11
10
9
8
7
WINDINGWIRE DETAILS
PRIMARY2
SCREEN 2
22
ENAMELLED COPPER WIRE
SECONDARY4
SECONDARY5
SECONDARY1
SECONDARY2
SCREEN 11 INSULATED 2mil COPPER FOIL
14
ENAMELLED COPPER WIRE
10
ENAMELLED COPPER WIRE (BIFILAR)
41
ENAMELLED COPPER WIRE
41
ENAMELLED COPPER WIRE
WINDING ARRANGEMENT ON BOBBIN
2 LAYERS MYLAR TAPE
PRIMARY2
SCREEN2
SECONDARY3+
SECONDARY5
+
SCREEN1
PRIMARY1
MATERIALS
ASSEMBLY DETAILS
DRAWING TITLE
DV78 450uH FLYBACK TX
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
COREPQ32/30 in PC44 MATERIAL (OR EQUIVALENT)
BOBBIN
CLAMPPART NUMBER TDK FPQ32/30-A (OR EQUIVALENT)
PART TO BE MARKED WITH PART NUMBER / ISSUE NUMBER
1
INTERNAL SCREENS TO BE FULL WIDTH. CONNECTION TO SCREEN VIA SOLDER JOINT TO COPPER (SEE DIAGRAM)
2
SOLDER JOINT TO BE ARRANGED TO PRODUCE A LUMP IN THE CORE WINDOW
SOLDER JOINT TO MADE MADE TO CLEAN COPPER AND JOINT TO BE TAPED.
SOLDER JOINT TO BE MADE HALF WAY ALONG LENGTH OF THE FOIL
SCREEN TO BE HIGHEST POSSIBLE RESISTANCE FOIL FOR LOWEST LOSSES. (I.E. FOIL AS THIN AS POSSIBLE)
SCREEN TO BE MADE FROM MAXIMUM 0.05mm (2MIL) FOIL
3 WINDINGS WILL BE A TIGHT FIT ON BOBBIN. NOTES AND WINDING ARRANGEMENT SPECIFIED TO BE ADOPTED.
4 TRANSFORMER TO BE FITTED WITH AN OUTER COPPER SCREEN WRAPPED AROUND THE OUTSIDE OF THE
OF THE TRANSFORMER CORE AND CONTACTING THE METAL CORE CLAMP THUS FORMING A SHORTED TURN
TO LEAKAGE FLUX. SEE DIAGRAM
SCREEN TO BE 10THOU COPPER STRIP 6 to 8mm WIDE AND FITTED OVER THE JOIN OF THE CORE HALVES.
SCREEN TO BE COVERED IN A LAYER OF TAPE.
5 PIN 1 ON BOBBIN TO BE MARKED WITH WHITE PAINT (OR OTHERWISE)
THIS MARKING TO BE USED TO ORIENTATE TX DURING WINDING PHASE TEST
6 100% PHASE TEST AND ISOLATION TEST TO BE CARRIED OUT ON ALL WINDINGS.
Filename:
Notes:
Contact Engineer:
CORE TO BE GAPPED IN CENTRE LEG TO GIVE REQUIRED Lpri (GAP APPROX 0.4mm)
(Lpri = 450uH +/- 10% PRIMARY INDUCTANCE MEASURED FROM PIN 1 TO 3 )
PART NUMBER TDK PC44PQ32/30Z-12 (OR EQUIVALENT)
PART NUMBER TDK BPQ32/30-1112CP (OR EQUIVALENT)
L925TX_1.1.Sch
Contact Tel: (01223) 203200Kevin Lamb
No PER
CABLE
1
1
2
1
1
0.72mm0.66mm
0.72mm0.66mm
0.3mm
START END
PIN #PIN #TURNS
321610.8mm 0.86mmENAMELLED COPPER WIRE
1 INSULATED 2mil COPPER FOIL
1112SECONDARY3
910
78
56
21PRIMARY11610.8mm 0.86mmENAMELLED COPPER WIRE
SLS06-10-03
KAL02-07-03
KAL21-03-0302_E086
KAL20-11-02
INITIALS
Printed:
DATE
8-Oct-2003
SPACE WINDING ACROSS WHOLE BOBBIN WIDTH
SCREEN TO HAVE NO OVERLAP AT ENDS
WIND ACROSS WHOLE BOBBIN WIDTH BETWEEN GAPS IN SEC4
SPACE WINDING ACROSS WHOLE BOBBIN WIDTH
WIND AS A BIFILAR PAIR ACROSS WHOLE BOBBIN WIDTH
WIND SEC1 AND SEC2 AS A BIFILAR PAIR ACROSS
WHOLE BOBBIN WIDTH
SCREEN TO HAVE NO OVERLAP AT ENDS
SPACE WINDING ACROSS WHOLE BOBBIN WIDTH
'VIEW FROM SIDE OF PART SHOWING PIN LENGTH DIMS' added.
1. To standards BS415 / EN60065 - Class I / EN60742
2. Transformer to be used in equipment which will be sold worldwide and certified to CE, CB, UL and CSA Standards. All
materials etc to be adequate for worldwide safety approvals.
11. Primary windings connect to 6 way MOLEX connector 39-01-2065. Secondary
44476-3112.
MOLEX connectors have pin numbers indicated on them.
12. Use 24 AWG wire with colours as shown. Primary wires are enclosed in a common
sleeve. Secondary wires are enclosed in a common sleeve. Use PVC sleeving.
13. Transformer to be marked with Arcam part number and issue number.
14. Transformer is for Hi-Fi audio; Acoustic noise must be inaudible.
15. Transformer to be supplied with mounting kit consisting of metal dished washer and 2 neoprene or similar washers.
115V ac
115V ac
6 WAY CONN PIN 1
6 WAY CONN PIN 4
6 WAY CONN PIN 3
6 WAY CONN PIN 6
PRIMARY
BROWN
WHITE
BLACK
BLUE
TOP VIEW
SECONDARY
RED
ORANGE
YELLOW
GREEN
4 WAY CONN PIN 2
4 WAY CONN PIN 1
4 WAY CONN PIN 4
4 WAY CONN PIN 3
SECONDARIES
PRIMARIES
TEST CIRCUIT
220MM, +20, -0
400MM, +20, -0
General Instrument / Vishay
W02G
W02G
FERRITE
3300UF
3300UF
Ferrite core WURTH 74270062 (or
equivelant).
Secondary wires pass through ferrite.
Heatshrink tubing fitted over ferrite, but
move along cable
4 way MOLEX 39-01-3048
or CONEXCON 6740-1040
+VOUT
120mA load
0V
120mA load
6 way MOLEX 39-01-2065
or CONEXCON 6740-1060
456
123
6 way
Pin-outs of Molex
connectors, as viewed
looking down at the end the
wires enter the connector
4 way
34
12
Voltage on Reservoir Capacitor
DRAWING TITLE
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
+VOUT_min
Minimum output voltage specified at:
Min input voltage
Max load
(see text)
0V
-VOUT_min
DV29 AUDIO TRANSFORMER
Filename:
Notes:
Contact Engineer:
L931TX_1.1.sch
-VOUT
65mm max
LEADS EXIT NEAR TOP
40mm max
Add 20mm to all lead lengths, ferrite free to move on cable1.121-07-04PG04_E107
Production release. Add ferrite core to secondary cable1.028-06-04PG04_E087
Reduce specified output voltage to 13.5V at 120mAA.127-04-04PG04_E048