Philips datasheet LD7523 Datasheet

LD7523

6/16/2009

Smart Green-Mode PWM Controller with Multiple Protections

REV: 00

General Description

The LD7523 is a low startup current, current mode PWM
controller with green-mode power-saving operation. T he
SOP-8/DIP-8 package integrated functions such as the
leading- edge blanking of the current sensing, internal
slope compensation, line compensation, and several
protection features. The protection functions include
cycle-by-cycle current limit, OVP, OLP, and brownout
protection. It provides the users a high efficiency, low
external component counts solution for AC/DC power
applications.

Furthermore, to satisfy various protection requirements,
both latch-mode protection and auto-recoverable
protection can be easily achieved by configuring LD7523
on different operation modes.

The special green-mode control is not only to achieve th e
low power consumption but also to offer a
non-audible-noise operation when the LD7523 is
operating under light load or no load condition.

Features

z High-Voltage CMOS Process with Excellent ESD

protection

z Very Low Startup Current (< 35μA)
z Current Mode Control
z Non-audible-noise Green Mode Control
z UVLO (Under Voltage Lockout)
z LEB (Leading-Edge Blanking) on CS Pin
z Internal Slope Compensation
z Programmable Line Compensation
z OVP (Over Voltage Protection)
z OLP (Over Load Protection)
z Brownout Protection
z Built in OLP De-Latch Timer
z 500mA Driving Capability

Applications

z Switching AC/DC Adaptor and Battery Charger
z Open Frame Switching Power Supply
z LCD Monitor/TV Power

Typical Application

EMI

AC
input

Filter

OVP

BNO

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LD7523-DS-00 June 2009

VCC

LD7523

GND COMP

1

OUT

CS

photocoupler

TL431

LD7523

O

P

Pin Configuration

Ordering Information

Part number Package TOP MARK Shipping

LD7523 GS SOP-8 Green Package LD7523GS 2500 /tape & reel
LD7523 GN DIP-8 Green Package LD7523GN 3600/tube /carton

SOP-8 & DIP-8(TOP VIEW)

OVP

VCC

OUT

7 6 5

TOP MARK

YYWWPP

1 8 2 3 4

BN

GND

CS

NC

COM

YY : Year code (D: 2004, E: 2005…..)
WW : Week code
## : Production code

The LD7523 is ROHS Complaint/ Green Package.

Pin Descriptions

PIN NAME FUNCTION

1 BNO

2 COMP

3 NC NC
4 CS Current sense pin, connect to sense the MOSFET current
5 GND Ground
6 OUT Gate drive output to drive the external MOSFET
7 VCC Supply voltage pin

8 OVP

Brownout Protection Pin. Connect a resistor divider between this pin an d bulk
capacitor voltage to set the brownout level and line compensation. When the
voltage of this pin fall below threshold voltage, the PWM output will be shut off.
Voltage feedback pin (same as the COMP pin in UC384X). Connect it with a
photo-coupler to close the control loop and achieve the regulation.

This pin is active-high to provide the OVP function. Connecting a zener or a
resistor voltage divider to Vcc will set the OVP level. Once the voltage rise
above 2.5V, the OVP will be tripped and the gate drive off. Short this pin to
ground to disable the OVP function.

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Block Diagram

LD7523

VCC

BNO

OVP

1.25V
/1.10V

2.5V

5.0V

Gain

= 0.04

Line

Compensation

Brownout

Comparator

OVP

Comparator

OLP

Comparator

65KHz

OSC

1 =OVP

OLP

Delay

PG

12.75V
/9.75V

1 = ACUV

1 =OLP

PG

internal bias

& Vref

UVLO

Comparator

SQ

PG

De-Latch

Counter

Auto Recoverable Protections

R

Driver
Stage

Vref OK

PG

VCC OK

OUT

Green- Mode

Vbias

COMP

CS

Control

Leading

Edge

Blanking

2R

R

0.85V

+

+

+

+

PWM

Comparator

Slope

Compensation

Line

Compensation

OCP

Comparator

GND

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SQ

R

LD7523

Absolute Maximum Ratings

Supply Voltage VCC -0.3V~30V
COMP, BNO, CS -0.3V ~7V
OUT
Maximum Junction Temperature 150°C
Operating Ambient Temperature Range -40°C to 85°C
Operating Junction Temperature Range
Storage Temperature Range -65°C to 150°C
Package Thermal Resistance (SOP-8) 160°C/W
Package Thermal Resistance (DIP-8)
Power Dissipation (SOP-8, at Ambient Temperature = 85°C) 400mW
Power Dissipation (DIP-8, at Ambient Temperature = 85°C) 650mW
Lead temperature (Soldering, 10sec)
ESD Voltage Protection, Human Body Model 2.5KV
ESD Voltage Protection, Machine Model 250V
Gate Output Current 500mA

-0.3V ~Vcc+0.3V

-40°C to 125°C

100°C/W

260°C

Caution:

Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

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LD7523

Electrical Characteristics

(TA = +25oC unless otherwise stated, VCC=12.0V)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage (VCC Pin)

Startup Current 20 35 μA

V

=0V 3.5 mA

Operating Current
(with 1nF load on OUT pin)

UVLO (off) 9.0 9.75 10.7 V
UVLO (on) 12.0 12.75 13.5 V

Voltage Feedback (Comp Pin)

COMP

V

=3V 2.7 mA

COMP

Protection Mode (note 1) 0.70 mA

Short Circuit Current V
Green Mode Threshold VCOMP 2.35 V

Current Sensing (CS Pin)

Maximum Input Voltage, V

Leading Edge Blanking Time 350 nS
Input impedance 1 NA MΩ
Delay to Output 200 nS

Gate Drive Output (OUT Pin)

Output Low Level VCC=15V, Io=20mA 1.0 V
Output High Level VCC=15V, Io=20mA 9.0 V
Rising Time VCC=15V,Load Cap.=1000pF 50 160 nS
Falling Time VCC=15V ,Load Cap.=1000pF 30 60 nS
Oscillator
Frequency 60 65 70 KHz
Green Mode Frequency 20 KHz

CS(OFF)

=0V 2.5 4.0 mA

COMP

V

=0V (note 2) 0.80 0.85 0.90 V

BNO

V

=1.30V 0.748 0.798 0.848 V

BNO

V

=3.75V 0.650 0.700 0.750 V

BNO

Frequency Temp. Stability (-40°C –85°C) 3 %
Frequency Voltage Stability (VCC=12V-30V) 1 %

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LD7523

Electrical Characteristics (Continued)

(TA = +25oC unless otherwise stated, VCC=12.0V)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Brownout Protection & Line Compensation (BNO Pin)

Brownout Turn-On Trip Level 1.20 1.25 1.30 V
Brownout Turn-Off Trip Level 1.05 1.10 1.15 V
Saturation Voltage on LINE Pin I
Line Compensation Ratio 0.04 V/V

Over Voltage Protection (OVP Pin)

OVP Trip Level 2.35 2.50 2.65 V
OVP de-bounce time 200 μS
Saturation Voltage on OVP Pin I

OLP (Over Load Protection)

OLP Trip Level V
OLP Delay Time V
OLP De-Latch Counter 500 mS

Soft Start

Soft Start Duration 5 7.5 10 mS

Note 1: When OVP, OLP Protection is tripped.
Note 2: Guaranteed by design because Vcs(off) can’t be measured when V

<1.5uA 5.0 V

BNO

<1.5uA 5.0 V

OVP

COMP(OLP)

COMP

4.5 5.0 5.5 V

>5.0V 60 mS

=0V.

BNO

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LD7523

y

Typical Performance Characteristics

15.0

12.0

14.0

13.0

12.0

U VLO (on) (V )

11.0

10.0

-40

0

40 80 120

T emperature (° C)

Fig. 1 UVLO (on) vs. Te mpera ture

70

67

64

61

11.2

10.4

9.6

UVLO (off) (V)

8.8

8.0

-40 040 80 120

Tempera ture (°C)

26

24

22

20

Fig. 2 UVLO (off) vs. T emperature

Frequency (KHz)

58

18

Green Mode Frequency (KHz)

55

-40 0 40 80 120

Temperature (°C)

Fig. 3 Frequency vs. Temperature

70

68

66

64

Frequency (KHz)

62

60

12 14 16 18 20 22 24

V

(V)

CC

Fig. 5 Frequenc

vs. VCC

16

-40

0

40 80 120

Temperature (°C)

Fig. 4 Green Mode Frequency vs. Temperature

25

23

21

19

17

Green Mode Frequency (KHz)

15

12 14 16 18 20 22 24

VCC (V)

Fig. 6 Green Mode Frequency vs. VCC

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LD7523

80

85

80

75

70

Max Dut y Cycle (%)

65

0.90

0.85
V

= 0V

LINE

0.80

V

=1.25V

V

LINE

LINE

=3.75V

(V)

0.75

CS (off)

V

0.70

0.65

60

-40 0 40 80 120

Temperature (°C)

Fig. 7 Max Duty Cycle vs. Temperature

40

30

20

Startup Current (μA)

10

0

-40 0 40 80 120

T emperature (°C)

Fig. 9 Startup Curr ent vs. Temperatu re

6.0

5.8

0.60

-40 0 40 80 120

Temperature (°C)

2.60

2.55

2.50

Fig. 8 Vcs (off) vs. Temperature

OVP (V)

2.45

2.40

-40 0 40 80 120

Temperature (°C)

5.5

5.3

Fig. 10 OVP-Trip Level vs. Temperature

5.6

5.1

(V)

COMP

5.4

V

5.2

5.0

-40 0 40

Fig. 11 V

COMP

120

Tem perature (°C)

open-loop voltage vs. Tem perature

4.9

OLP (V)

4.7

4.5

-40

0 40 80 120

Temperature (°C)

Fig. 12 OLP-Trip Level vs. Temperature

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LD7523

3

4

10

8

10

8

6

4

(μA)

LINE

I

2

0

-2
0 1 2 3 4 5

V

LINE

Fig. 13 V

1.27

1.26

1.25

LINE

vs. I

LINE

BNO Pin On (V)

1.2

1.2

-40 0 40 80 120

Temperature (°C)

Fig. 15 BNO Pin On Level vs. Tem pe rat ure

125°C

25°C

-40°C

6

4

(μA)

OVP

I

2

0

-2

0 1 2 3 4 5

V

OVP

1.150

1.125

1.100

Fig. 14 V

OVP

vs. I

OVP

125°C

25°C

-40°C

BNO Pin Off (V)

1.075

1.050

-40 0 40 80 120

Temperature (°C)

Fig. 16 BNO Pin Of f Level vs. Temper ature

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LD7523

Application Information

Operation Overview

As long as the green power requirement becomes a trend
and the power saving is getting more and more important
for the switching power supplies and switching adapters,
traditional PWM controllers are not able to support such
new requirements. Furthermore, the cost and size
limitation forces the PWM controllers to powerfully
integrate more functions for reducing the external part
counts. The LD7523 is targeted on such applications
and provides an easy and cost effective solution; its
detailed features are described as below.

Under Voltage Lockout (UVLO)

An UVLO comparator is implemented in it to detect the
voltage on the VCC pin, for assuring the supply voltage
high enough to turn on the LD7523 PWM controller and to
drive the power MOSFET. As shown in Fig. 19, a
hysteresis is built in to prevent the shutdown due to the
voltage dip during startup. The turn-on and turn-off
threshold levels are set at 12.75V and 9.75V,
respectively.

Vcc

UVLO(on)

Startup Current and Startup Circuit

The typical startup circuit for the LD7523 is shown in Fig.

20. During the startup transient, the Vcc is lower than
UVLO threshold and thus there is no gate pulse produced
from the LD7523 to drive power MOSFET. Therefore, the
current through R1 will provide the startup current and to
charge the capacitor C1. Once upon the Vcc voltage is
high enough to turn on the LD7523 and further to deliver
the gate drive signal, the supply current is provided from
the auxiliary winding of the transformer. Lower startup
current requirement for the PWM controller will help to
increase the maximum value on R1 and then reduce the
power consumption on R1. By using CMOS process and
the special circuit design, the maximum startup current of
LD7523 is only 35μA.
If a higher resistance value of the R1 is chosen, it usually
takes more time to start up. To carefully select the value of
R1 and C1 will optimize the power consumption and
startup time.

AC
input

EMI

Filter

Cbulk

R1

D1

UVLO(off)

t

I(Vcc)

startup current
(~uA)

Fig. 19

operating current
(~ mA)

t

Output Stage and Maximum Duty-Cycle

An output stage of a CMOS buffer, with typical 500mA
driving capability, is incorporated to drive a power

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LD7523

Fig. 20

VCC

GND

C1

OUT

CS

LD7523

MOSFET directly. And the maximum duty-cycle of
LD7523 is limited to 75% to avoid the transformer
saturation.

Oscillator and Switching Frequency

The switching frequency of LD7523 is fixed as 65KHz
internally to provide the optimized operations by
considering the EMI performance, thermal treatment,
component sizes and transformer design.

Voltage Feedback Loop

The voltage feedback signal is provided from the TL431 in
the secondary side through the photo-coupler to the
COMP pin of LD7523. The input stage of LD7523, like
the UC384X, has 2 diodes voltage offset before feeding
into the voltage divider with 1/3 ratio, that is,

1

+

COMPARATOR

A pulling-high resistor is embedded internally to eliminate
the requirement of another resistor in the external circuit.

)V

3

Dual-Oscillator Green-Mode Operation

There are many different topologies implemented in
different chips for the green-mode or power saving
requirements, such as “burst-mode control”,
“skipping-cycle mode”, “variable off-time control “…etc.
The basic operation theory of all these approaches
intends to reduce the switching cycles under light-load or
no-load condition either by skipping some switching
pulses or reduce the switching frequency.

By using this dual-oscillator control, the green-mode
frequency can be well controlled and further to avoid the
generation of audible noise.

)V2V(

−×=

FCOMPPWM(

the LD7523, the internal slope compensation circuit has
been internally implemented to simplify the external circuit
design.

Current Sensing, Leading-Edge Blanking

The typical current mode PWM controller feedbacks both
current signal and voltage signal to close the control loop
and achieve regulation. The LD7523 detects the primary
MOSFET current from the CS pin, which is not only for the
peak current mode control but also for the pulse-by-pulse
current limit. The maximum voltage threshold of the
current sensing pin is set as 0.85V. Thus the MOSFET
peak current can be calculated as:

I

A 350nS leading-edge blanking (LEB) time is included in
the input of CS pin to prevent the false-trigger from the
current spike. However, the total pulse width of the
turn-on spike is decided by the output power, circuit
design and PCB layout. It is strongly recommended to
adopt a smaller R-C filter (as shown in figure 21) to avoid
the CS pin being damaged by the negative turn-on spike.

=

)MAX(PEAK

−

R

S

)V85.0(

ONCOMPENSATI_LINE

Internal Slope Compensation

A fundamental issue of current mode control is the
stability problem when its duty-cycle is over 50%. To
stabilize the control loop, slope compensation is required
in the traditional UC384X design by injecting the ramp
signal from the RT/CT pin through a coupling capacitor. In

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Fig. 21

LD7523

Brownout Protection & Line Compensation

Line Voltage

The LD7523 employs BNO pin to set the brownout
protection point and the line voltage OVP point though
BNO pin.
The voltage across the BNO pin is proportional to the bulk
capacitor voltage, referred as the line voltage. A
brownout comparator is implemented to detect the
abnormal line condition. As soon as the condition is
detected, it will shut down the controller to prevent the
damage. Figure 22 shows the operation. When V

BNO

falls below 1.25V, the gate output will be kept off even Vcc
has already achieved UVLO(ON). It therefore makes Vcc
hiccup between UVLO(

) and UVLO(

ON

line voltage is large enough to pull V

). Unless the

OFF

larger than 1.25V,

BNO

the gate output will not start switching even when the next
UVLO(ON) is tripped. A hysteresis is implemented to
prevent the false trigger during turn-on and turn-off.

Meanwhile, LD7523 detects the voltage across BNO pin
to feed the line compensation signal to the current sense

1.25V

1.10V

UVLO(on)
UVLO(off)

V

BNO

Vcc

OUT

t

AC OK area

t

t

SwitchingNon-Switching

t

Fig. 22

V⋅2

ac

circuit. Figure 23 shows the circuit. The OCP level of
high-line and low-line can be set to a very close point.

The voltage gain from the BNO voltage to line
compensation is 0.04 (V/V). The relationship between
BNO pin voltage and the line compensation is illustrated
in figure 24.

∑

Fig. 23

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LD7523

Line
Compensation

160mV
150mV

Linear Region

gain=0.04

52mV

Turn-Off

Region

1.30V

Fig. 24

Over Load Protection (OLP)

3.75V

4.0V

By using such protection mechanism, the average input
power can be reduced to minimum level to control the
component temperature and stress within the safety
operation area.

VCC

OLP Delatch by UVLO(off)

V

pin1

UVLO(on)

UVLO(off)

Over Load

Over Load

T

COMP

To protect the circuit from damage under over load
condition or short condition, a smart OLP function is
implemented in the LD7523. Figure 25 shows the
waveforms of the OLP operation. In such cases, the
feedback system will force the feedback voltage loop
toward the saturation and pull the voltage of COMP pin
(VCOMP) to high. Once the VCOMP trips the OLP
threshold of 5.0V and stays for more than 60mS, the
protection will be activated and then turns off the gate
output to stop the switching of power circuit. The 60mS
delay time is to prevent the false trigger from the power-on
and turn-off transient.

The Fig. 26 shows the other application example. The
VCC of LD7523 will be supplied by an auxiliary source
voltage (e.g. standby power) instead. Once the voltage of
COMP pin trips the OLP threshold voltage (5.0V) and
stays for more than 60mS, OUT pin will stop switching
soon. The VCC voltage will not descend since VCC is
supplied by an auxiliary voltage source. Otherwise, the

OLP Delay Time

5V

OLP Delay Time

T

OUT

Switching

Switching

Non-Switching

Switching

T

Fig. 25

internal OLP de-latch counter will active and count for a
skipping duration (500mS). It is called as OLP SKIP
DURATION. The OUT pin will stop switching until the OLP
de-latch counter is reset and then resume to normal
switching.

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LD7523

R

VCC

OLP Delatch by
Internal Counter

Vbulk-cap

UVLO(on)

UVLO(off)

Over Load

OLP skip duration

Over Load

T

COMP

OLP Delay Time

5V

OLP skip duration

OLP Delay Time

T

OUT

Switching

Switching

Non-Switching

Switching

T

Fig. 26

Over Voltage Protection (OVP)

To prevent the component from damage due to fault
condition, LD7523 is implemented with protection through
the OVP pin. Figure 27 and figure 28 show 2 different
configurations to program the OVP setting point --- zener
detection and voltage divider. It provides zero bias
current during normal operation so that it will not affect the
startup timing, as figure 27. But the tolerance of OVP trip
point will be larger due to the distribution of the breakdown
voltage of zener diode.
On the other hand, using the circuit of figure 28 will be
beneficial from the minimum cost and higher OVP
accuracy, but it requires larger value of R1 and R2 to
avoid affecting on startup timing by the load effect.
As shown in figure 29, if the voltage on the OVP pin rise
above threshold voltage of 2.5V, the output gate drive
circuit will be shutdown simultaneous in order to stop
switching the power MOSFET. But if the voltage on the
OVP pin drops below 2.5V, it will automatically resume to
the normal operation on the next UVLO(on) level.

OVP Level

UVLO(on)

UVLO(off)

V(OVP)= Vz+2.5V

VCC

OUT

Switching

Vz

OVP

Fig. 27

VOVPV +⋅=

1(5.2)(

Fig. 28

OVP Tripped

Non-Switching

Fig. 29

VCC

LD7523

R

2

)

1

GND

t

Switching

t

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LD7523

Summary of Protections

There are several ways to control the on/off of LD7523.
The details are listed as the table below.

Turn Off Operation
COMP

OLP

OVP

Brownout

Comp Pin <

1.4V
Comp Pin >

5.0V
OVP Pin >

2.5 V
BNO Pin <

1.25V with
Hysteresis

Cycle by Cycle Mode
Non-latch
Hiccup Mode
Non-latch
Re-start after next
UVLO(on)
Cycle by cycle mode
Non-latch

Table 1

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Package Information

SOP-8

Symbols

LD7523

Dimensions in Millimeters Dimensions in Inch

MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053

H 0.178 0.229 0.007 0.009

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

θ 0° 8° 0° 8°

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Package Information

DIP-8

Symbol

LD7523

Dimension in Millimeters Dimensions in Inches

Min Max Min Max

A 9.017 10.160 0.355 0.400
B 6.096 7.112 0.240 0.280
C ----- 5.334 ------ 0.210
D 0.356 0.584 0.014 0.023
E 1.143 1.778 0.045 0.070
F 2.337 2.743 0.092 0.108

I 2.921 3.556 0.115 0.140
J 7.366 8.255 0.29 0.325

L 0.381 ------ 0.015 --------

Important Notice

Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.

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Revision History

Rev. Date Change Notice
00 6/16/2009 Original Specification.

LD7523

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