Page 1
ЭЧОЭЛЧМ ЬЧЯЩЯУ МЛТЫО ЮСЯОЬ
тттттттттттттттттттттттттттттттттттттттттттттттттттттз
CEM3000B
прупп
поупн
пмупл
пкупй
МЛТЫО ò
TROUBLE SHOOTING.................................................................21-22
è
ïç
îð
2011-11-17
Page 2
METHOD OF DISASSEMBLING CEM3000B
The procedure of disassemblin钮 the unit
1) Press EJ button and take out paneltake out A screw in top cover of the unit;Use tweezer to prize up top cover as the blue arrow direction which showed as below picture
A
EJ
2 Use electrical screw bit to take out B,C two screws in left and right side of metal bracket; Then take out D,E screws in panel base
B
3Uplift the CD deck mechanism and take out FFC then take out deck mechanism
C
D
E
The procedure of disassemblin钮 the panel:
1Use electrical screw bit to take out five screws in back panel and separate back panel and front panel; Take out the back panel and then take out
KB board.
Page 3
3
Page 4
ЙЧОЧТЩ ЬЧЯЩОЯУ
ì
Page 5
CIRCUIT DIAGAM MAIN BOARD
102
C67
IN4007
4K7
EC28
C88
C61
474
474
R155
Q2
882
OPTIONAL
1UF
R122
4K7
474
R123
4K7
474
R124
4K7
R125
4K7
4
R187
NC
R199
220
C122
ZD6
104
6V8
R176
2K2
Q15
C108
R223
9014C
NC
NC
R222
Q14
C114
9014C
NC
NC
R221
Q12
9014C
Q13
9014C
R88
10K
22
11
12
15
14
13
4
S GND
EC31
47UF
AUTO_AINT
C116
NC
NC
R220
C127
NC
NC
EC22
2200UF
6
20
1
U3
4702
10
16
ILLUME_IN
F/R-
F/L+
F/L-
R/R-
R/L-
+9V
9015
Q37
R178
22K
R177
1K
CON10
AV-4P
D
1
2
3
4
5
6
C
Q36
9014C
C16
F LINE R
0
C18
F LIME L
0
C15
R LINE R
0
C17
R LINE L
0
C92
104
9
8
7
5
2
3
17
18
19
21
24
23
C107
474
F/R+
R/R+
R/L+
B
A
5
321
L102
ANT
1.8uH
L101
EC48
2.7uH
C99
47UF
TP31
ANTENNA
D
C
C87
R115
5K6
152
CN9
1
R105
1K5
2
3
R116 1K5
4
5
6
7
100
R128
8
100
R129
9
100
R130
10
100
R131
11
12
R132 100
13
14
15
16
17
18
19
B
20
R92 100
21
R10 NC
22
23
24
CON24-2.0
CN1
2p-2.0mm-R
A
TUNER TDA7703/7703R
GRF
FMANT
AMANT
GRF
VRF
GND
VIF
GND
VCDIG
D8
D15
D20
9015S
D26
EN7418
GNDGNDGND
L11
FBL5FB
DACOUT-L
C206
104
EC13
100UF
L9
FB
R218
10K
R211
3K9
D11
EUR
RDS ON/OFF
UP01
TX
6
RX
7
8
CPU UPGRADE SOCKET
RES
1234567891011 12 13 14 15
GND GND GND GND
C210
C209
104
104
EC51
EC14
100UF
100UF
C84
R108
5K6
152
Q40
S5V
VOL+9V
CD_L
CD_R
S5V
D7
SENSI_IN
DIS RDS
CDP_RST
D16
MP3_C LK
DIS AUX(CEM3000B)
MP3_D I
EN TA ON(CEM3000)
MP3_D O
D18
EN 2COLOR
D27
N.C
TUNER19A(for CEM3000)
FEEDF
MP3_R EQ_ O
FEEDR
USB/SD _DE T
USB_DN
USB_DP
CD ON
MP3_R EQ_ 1
C5V
MIC-
MIC+
CPU5V
S1
RES SW
R159
10K
ZD5
3V3
U13
R86
+9V
C47
1R 1W
104
LA7809
out
EC2
gnd
100UF
1 2 3 4
R287
47K
Q16
DACOUT-R
SDA
SCL
RDSINT
RSTN
R17
RA-R
3K3
R12
RA-L
3K3
R57
R53
C7
R13
47K
20K
20K
R77 220
R19 220
R16 100R
R213 100
R154
RA SDA
10K
RDS_CLK
RA SCL
RSTN
MCU 34Pin
C9
DAB_ANT POW
272
272
BEEP/IN3
MP3_REQ_1
9015
VCC
R283
22K
R285
4K7
Q17
9014
MP3_CLK
MP3_DI
MP3_REQ_O
FEEDF
CD ON
CDP_RST
MP3_DO
CPU5V
SENSIO
CPU5V
R207
BEEP/IN3
AREA 1
D14
DIS AM
D23
EN SUB-W
D25
AREA 3
NCVPP
45
+5V
3
X IN
2
GND
1
Q32
9015S
10K
R188
in
EC1
100UF
POWER_IN2
5V_POW_IN1
DIMMER
R203
220K
RESET
BT_RX
BT_TX
VPP
CPU5V
R217
22K
R94
2R2
C44
104
OUT1
OUT2
OUT3
RESET
C104
220k
R208
R204
220K
POWER_IN2
5V_POW_IN1
OUT3
OUT2
OUT1
RESET
DIMMER
VPP
R148
4K7
7.2MHz
XT4
C112
CPU5V
104
C129
104
ACC_DET
SCL
SDA
LAMP_POW
VCC
R78
4K7
220K
1
IN2/POWER
2
IN1/5V_POW
3
DIO OUT3
4
DIO OUT2
5
DIO OUT1
6
RESET
7
NC
R142
100R
8
UP
9
FLDM0
10
X-IN
C113
30P
X-OUT
11
30P
12
REGC
13
GND
GND
14
15
VDD
16
VDD
C128
4U7
USB_5V
USB_DN
VOL_LED
USB_DP
SYS5V
CN5
CON22-2.0P
60
FEEDF
MP3_DI
CD-ON
CDPRES
MP3_DO
BEEP/IN3
MP3_REQ1
ACC_DET
17 18 192021 22 23 24 25 26 27 28 29 30 31 32
BT_LED
F_INH
LAMP_VCC
MP3_CLK
MP3_REQ
U1
CEM3000
33Pin:REMOCONIN
FDATA
FCLK
LAMP_POW
VOL_SCL
VOL_CLK
FRONTINH
NC
2COLOR
F_CLK
F_CE
F_DATA
10111213141516171819202122
FRONTCE
RN1
4K7
F_DATA
F_CLK
F_INH
F_CE
AUX_R
REMOTE
KEY1
KEY2
ENCODER
CPU5V
104
R103
U10 I C1. 2V
0
IN
EC23
NC
C141
EC41
104
47UF
RA/DAB+
C150
104
R216
47K
USB/SD_DET
CPU5V
CPU5V
ENCODER
FEEDR
SENSI_IN
KEY1
R234 10K
R127 4K7
R104
330K
R24
1K
54
FEEDR
DANCE
CDP_SW
KEYADI1
ENCODER
USB/SD_DET
NC
USB_POW
NC
BT_LED
2COLOR
R174
R26
NC
NC
R175
0
2COLOER
USBPO
BT_LED
RA_RST
C5V
AUX_L
BATT+
EC21
EC7
220UF
C111
104
EC110
220UF
123456789
+3V3
GND
GNDNCNCNCNCNCNC
+1.2V
11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
L30
L29
FB
0
EC50
OUT
KEY2
R206
R205
470K
4950515253555657585961626364
KEYADI2
RA_SDA
RA_SCL
BT_MUTE
BT_TXD
BT_RXD
SENSIO
MUTE
RA_RES
RDS_INT
220UF
GND
123
EC40
C142
100UF
104
EC38
220UF
U14
LA7805
in
out
EC3
gnd
47UF
C12
102
NC
1M
R194
CPU5V
NC
R93
1K
R193
102
C124
5V6
ZD1
ZD2
5V6
AGND
48
VDD
47
R18
46
1K
R15
45
1K
44
43
42
41
NC
40
R179
4K7
39
NC
38
NC
37
FLASH
36
35
NC
NC
34
33
RDS_CLK
C121
R82
R120
1K
1M
22P
REMOTE
C125
104
L2
100uH/2A
R111
0R 1W
C152
C20
220UF
103
U9 IC3.3V
IN
GND
OUT
EC37
123
47UF
R32
0R 1206
C143
C3
103
103
VCC
EC5
C151
104
47UF
47K
R195
CPU5V
ENCODER
R197
330K
RA/DAB+
R20
R21
4K7
4K7
CPU5V
RA_SDA
RA_SCL
DAB_TX
DAT_RX
SENSIO
DAB_RESET
MUTE
LED11
NC
R186
DAB_ANT POW
4K7
CPU5V
EC33
47UF
EC42
电池
NC
R119
123
R145
33R
1K
EC107
C126
220UF
104
TUN1 DAB-TUN
NCNCRXTXNCNCRESETNCNCNCNCNCNC
NC
NC
R266
2K2
33P
R4
1K
R288
330R
R264
1R
EC9
100UF
CPU5V
DAB_TX
DAT_RX
DAB_RESET
RA-L
RA-R
C89
CD_L
C86
4U7
CD_R
C68
4U7
CREF
GND
R2681KR267
NC
C204
R31
R30
10R
10K
Q204
9014S
R271
47K
4U7
C77
C83
C78 1UF
C410
1UF
1UF
4U7
1011121314 15
SE1L
SE1R
SE2R
DIFR/SE0R
DIFFG
OUTSW/OUTRL2
OUTRF
16171819202122232425262728
SE2L
DIFFL/SE0L
U5
TDA7419
OUTLR
OUTRR
OUTLF
MUTE
SCL
R112
R191
4K7
C5V
4K7
SUB_OUT
R192
SCL
SDA
R121
VOL+9 V
R170
AUX_R
1K
R189
10K
R185
R190
10K
AUX_L
1K
Q34
9015
BAT+ SUB_MUE
R162
10K
R163
4K7
R164
4K7
R102
NC
C120
EC36
C100
104
47UF
SYS5V
ACC_DET
SUB_OUT
5V_POW_IN1
U8 AP1507
VIN
OUTPUT
GNDFBSD
R79
47K
D130
SK24
4
C145
10UF
R265
R286
EC111
2K2
5
10UF
R52
4K7
Q105
9014S
GND
2K2
RR
FL
RL
FR
L3
15nH
2R2
C140
4U7
C118
222
C117
222
C139
4U7
Q31
9014
U4
LM2950
IN
GND
OUT
100 1/2W
104
ZD7
30V
R201
1K
C123
R202
22K
102
OPTIONAL
153
22K
C146
683
C502
R279
R273
47
22K
EC112
220UF
R278
39K
Q11
R280
2K2
9014
SUB_MUE
NC
NC
A-GND
L-CH
R-CH
27 28 29 30
C134
C144
0
0
R261
R260
1K5
1UF
C91
1UF
SE3R/ACINR
SDA
1K5
R269
10K
R270
330
Q203
9014S
R96
R97
0
0
123456789
AC/AC2OUTR
SE3L/ACINL
ACOUTL/AC2OUT
ACINL/FILOL
ACINR/FILOR
MIX/SW/OUTRR2
SAOUT
VREF
SAIN
VDD
C5
104
R114
2K2
C5
EC24
104
100UF
C73
R101
1K
104
Q41
R49
882
C46
102
R183
EC39
C119
104
100UF
Q35
9015
Q30
9014
R274
39K
123
4
IC104
NM4558
470
EC43
47UF
R5
100 1/2W
R161
5678
R281
2K2
EC45
ZD10
100UF
9V1
EC15
100UF
Q9
SI2301BDS
R228
1K
Q8
9014S
R167
4K7
1K
C109
104
C149
R275
104
62K
EC113
R276
C148
220
100UF
474
R277
10K
C147
103
LAMP_VCC
DIMMER
R157
ILLUME-IN
R262
2K2
R263
2K2
C101
272
C102
272
AUX/R
AUX/L
AUX R
AUX L
R72
1R 1W
USB_5V
R42
10K
R227
USBPO
4K7
ZD3
6V8
R152
10K
R284
22
EC279
100UF
CON6
2PIN
R282
2K2
Q10
9014
NC
LAMP-POW
MUTE_1
R85
NC
R146 NC
R67 NC
R73
FR
NC
EC30
NC
R149
NC
R66 NC
R71
NC
FL
R81
NC
VCC
BC
R65
R63 NC
NC
R61 NC
R75
NC
RR
EC20
NC
NC
R64
R60 NC
R74 NC
RL
R68
NC
MUTE1
C93
RR
RL
C115
FL
4U7
C95
FR
BEEP
VCC
C21
104
C5V
VCC
1
2
MUTE1
MUTE
VCC
C19
104
VCC
POWER_IN2
Q27
R141
4K7
C136
104
U11
78L15
IN
2.2 1/2W
A1273
R255
4K7
C34
104
R153
10k
D12
NC
R29
NC
C39
NC
5678
NC
U6
4
C38
NC
R14
NC
C37
5678
NC
U7
4
NC
C36
4U7
C94 4U7
4U7
R89
1K
9015S
R140
47K
Q28
9014S
GND
OUT
RESETTABLE FUSE
R155
C41
R168
104
22K
R1
2K2
123
123
NC
Q25
Q33
9014C
R169
4K7
OPTIONAL
D24
4148
R139
4K7
EC46
NC
NC
EC19
R69
C35
NC
NC
R55
NC
R45
180
R58 NC
C32
NC
NC
EC18
R54
NC
R84
10K
R107
1K
R99
1K
R100
2K2
VCC
R156
BATT+
R196
R160
2K2
ZD4
4V7
Q38
9014C
R158
47K
EC12
R3
10UF
220
R37
R36
4K7
EC11
R2
10UF
220
C79
10UF
R35
4K7
R44
180
R50
4K7
C80
10UF
Q23
9014C
C137
NC
R118
1K
R117
C90
47K
R113
220K
102
C85
C82
R109
R110
47K
220K
C57
R95
R91
102
220K
47K
C708
R98
R90
102
47K
220K
R144
10K
C98
1UF
EI-14
L1
D1
5401
123456789101112131415
ACC_IN
CON2
ISOCON
Page 6
CIRCUIT DIAGAM SERVO BOARD
ê
Page 7
GND
USB_UP
USB_DN
USB_5V
GND
SYS_5V
BT_LED
LAMP_VCC
INH
DATA
CLK
CE
2COLOR
REMOTE
ENCODER
+5V
GND
KEY2
KEY1
AUX_R
AUX_L
GND
ЭЧОЭЛЧМ ЬЧЯЩОЯУ РЯТЫФ ЮСЯОЬ
Q903 Q901 Q902
R957
DO
CLK
CE
M1
R955
B
G
R
DO
LCK
R956
M2
M3
SUB/DBB
EQ
CE
GND
D1
D2
ipod
SC6579
TRACK-UP TRACK-DN
3K3 4K7
M4
R913
8K2
M5
M6
DISP
POWER/MUTE
BANDAUDIOMENU
EJ
VOL+
VOL-
1 0F 1
Page 8
CIRCUIT DIAGAM REMOTE BOARD
Page 9
ЭЧОЭЛЧМ ЬЧЯЩОЯУ МЛТЫО ЮСЯОЬ
5 4 3 2 1
C5
100nF
C3
1UF
C7
1UF
1
2
GND-RF
33
VCC-DAC
32
GND-1V2
31
IC1
R9
L10
C42
68pF
R10
VDD-1V2
RDSINT
VDD-1V2
VDD-3V3
REG-1V2
VCCREG12
L11
RSTN
30
L16
29
28
27
SCL
26
SDA
25
24
23
C41
C43
100nF
R12
33 1/2W
C2
470nF
C13
100nF
C40
1uF
DACOUT_R
DACOUT_L
RSTN
RDSINT
C39
10nF
L4
L17
1uH
LQM21PN1R0MC00
MuRata
1uF
C46
JP2
VDIG
C14
C22
100nF
R4
R6
SCL
SDA_MOSI
GND-RF
FMANT
AMANT
GND-RF
VDIG
DACOUT_L
DACOUT_R
SDA_MOSI
RDSINT
RSTN
JP3
1
2
3
VRF
GND
VIF
GND
SCL
4
5
6
7
8
9
10
11
12
13
14
15
Header 15
D
C
B
100nF
10
11
1
2
3
4
5
6
7
8
9
LF1
TCAGCFM
FMMIXDEC
FMMIXIN
GND-RF
FMPINDRV
VCC-RF
TCAM
PINDDEC
PINDIN
GND-LNA
10nF
C34
1uF
L1
L3
C4
C44
R11
C45
10nF
100nF
TQFP44 pins 10x10 I.C. and SMD socket
C35
100nF
D
VIF
C6
GND-RF
C8
4.7nF
C15
9018
C
GND-RF
Q1
9018
FMANT
B
C24
TOKO
L5
VRF
AMANT
R8
220
L7
Q2
C19
C25
C33
C20
10nF
100nF
GND-RF
R7
1uF
C18
10nF
GND-RF
C21
2.2uF
C9
C26
1uF
C32
C10
L8
NOTES:
or TDK MMZ1608Y152C
A
VDIG
A
12345
ç
Page 10
УЯЧТ РЭЮ ЭСУРСТЫТМ ФЯЗСЛМ ЮСММСУ НЧЬЫ КЧЫЙ
10
Page 11
УЯЧТ РЭЮ ЭСУРСТЫТМ ФЯЗСЛМ МСР НЧЬЫ КЧЫЙ
11
Page 12
SERVO PCB COMPONENT LAYOUT TOP SIDE VIEW
12
Page 13
SERVO PCB COMPONENT LAYOUT BOTTOM SIDE VIEW
Page 14
PANEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW
14
Page 15
PANEL PCB COMPONENT LAYOUT TOP SIDE VIEW
Page 16
REMOTEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW
Page 17
REMOTEL PCB COMPONENT LAYOUT TOP SIDE VIEW
17
Page 18
TUNER PCB COMPONENT LAYOUT BOTTOM SIDE VIEW
18
Page 19
ЧНС РЭЮ ЭСУРСТЫТМ ФЯЗСЛМ
19
Page 20
SET EXPLODER VIEW DRAWING
20
Page 21
Product Model
NO.
failure
phenomena
Trouble shooting
Trouble shooting
Trouble shootingTrouble shooting
CEM3000B
Area All area
Tate
failure cause remark
a. To check whether it is connect well of the ISO connector (4 PIN power input ). Whether it is loose of the 15A fuse of the
ISO connector, or insert non in place.
b. To check whether there is any contamination and bad contact on the 22 Pin male/female connector on the panel and main
board.
c. To check the power supply of main board B+ACC should be +12V; The voltage of stabilivolt of ACC power supply circuit
ZD3 (6V8) should be 6V8.
2011-11-16
NO Power
1
NO audio
2
output
d.To check the voltage of the 17 pin of U1 MCU should be +4V8.
e. To check the voltage of the 16 pin (AVDD) of U1 MCU (T5CL8) should be +5V; The output voltage of U4 (LM2950) should
be +5V.
f. To check the oscillation frequence of crystal XT4 shuold be 7.2MHz .
g.To check the resistor network of NR1 (4K7).
H. To check the voltage of the15 pin(Lamp Vcc) of CN5 should be 6V4.
a. To check whether the volume knob is turn to the minimum position.
b. To check whether the unit is at MUTE mode, press SOURCE button and check whether it is effective of the input sound
source.
c. To check whether the connection of 8 PIN audio output wire of ISO connector is correct; wrong connection or short circuit
to the ground will caused the protection of the power amplifier( no voltage output).
d . To check the circuit of power amplifier U3 (LV47002) and VOLUME U5(TDA7419).
e. To check the normal voltage of 22 PIN(MUTE) of power amplifier U3(LV47002) , normally should be 4V.
f. To check the voltage of 20 pin of audio processor U5TDA7419, should be +9V0.
g. To check the voltage of control PIN SCLSDAthe 1819 pinof audio processor U5TDA7419, should be +5V2.
3
AM/FM
Radio
abnormal
a. To check the antenna of the AM/FM tuner.
b. To check whether the strength of then input signal of the tuner is too weak.
c. To check the voltage of the 5 pin7 pin9 pin of the tuner, should be +5V0
d. To check the voltage of the 12 pin(SDA) of the tuner, should be +4V5; the 13 pin(SCL) should be +4V5; the 15 pin(RA-
RES) should be +4V9.
e. To check the L output voltage of the 10 pin of tuner should be 1V8, the 11 pin R output voltage , should be 1V8.
21
Page 22
NO.
failure
phenomena
failure cause remark
a. To check the antenna of the DAB tuner.
4
5
DAB Radio
CD defective
abnormal
b. To check whether the strength of then input signal of the tuner is too weak.
c. To check the supply voltage of the 1 pin of TUN1DAB-TUN should be +1V2the 2 pin should be +3V3.
a. To check whether the signal format of the disc is correspond to the request of the unit, whether there is any
contamination or damage or light leakage on the surface of the disc.
b. To check whether there is any abnormal of the rotation of the deck mecahnism, or whether the disc is enter in
position.
c. To check whether it is normal when reading USB?
d. To check whether the 17 P FFC of laser pick up is inserted in place, whether the socket of it is loose.
e. To check whether there is any contamination or foreign body on the surface of the laser pick up.
f. To check the servo board connector of CN20P1 and main board connector of CN9, whether the socket of it is loose.
j. To check the switch SW2 on the servo board.
h. To check the rotation mechanism of CD deck mechanism.
i. To check whether the rotation belt of deck mechanism is dislocation or loose.
6
USB/iPOD
defective
7 AUX defective
a. To check whether the USB/iPOD signal format is correspond to the request of the unit.
b. To check the voltage of the the uppermost pin of the USB connector, should be +5V.
c. To check whether there is any wearing and scratch of the shrapnel and pin of the panel USB.
d. To check whether there is any contamination and bad contact on the male/female connector of the panel and main
board. If necessary, can exchange the panel to test whether the defective is occurred by the unit or panel.
a. To check the SOURCE shoule be in MP3-LINK mode.
b. To check the AUX IN input signal.
c. To check whether there is any contamination and bad contact on the male/female connector of the panel and main
board. If necessary, can exchange the panel to test whether the defective is occurred by the unit or panel.
22
Page 23
TENTATIVE Version No.18052009
LV47002P Development Specification Proposal
(BTL 4 channel Car Audio Power Amplifier)
The LV47002P is the IC for 4-channel BTL power amplifier that is developed for car audio system.
Pch DMOS in the upper side of the output stage and Nch DMOS in the lower side of the output stage are
complimentary. High power and high quality sound are realized by that.
This IC incorporate various functions (standby switch, muting function, and various protection circuit) necessary for
car audio system. Also, it has a self-diagnosis function.
1. Application : 4-channel BTL power amplifier for car audio system
2. Package type : HZIP25
3. Functions and Features :
- High power : - Pomax=48W (typical)
(Vcc=15.2V, f=1kHz , JEITAmax , RL=4Ω)
- Po = 28W (typical)
(Vcc=14.4V, f=1kHz , THD=10% , RL=4Ω)
- Po = 21W (typical)
(Vcc=14.4V, f=1kHz , THD=1% , RL=4Ω)
- Built-in muting function (pin 22)
- Built-in Standby switch function (pin 4)
- Built-in Self-diagnosis function (pin 25) : Signal output in case of output offset detection, shorting to VCC,
shorting to ground , and load shorting.
- Electric mirror noise decrease
- Built-in various protection circuit (shorting to ground, shorting to VCC, load shorting, over voltage and
thermal shut down )
- No external anti-oscillation part necessary.
Note1 : Please do not mistake connection.
A wrong connection may produce destruction, deterioration and damage for the IC or equipment.
Note2 : The protective circuit function is provided to temporarily avoid abnormal state such as incorrect output
connection. But, there is no guarantee that the IC is not destroyed by the accident.
The protective function do not operate of the operation guarantee range. If the outputs are connected
incorrectly, IC destruction may occur when used outside of the operation guarantee range.
Note3 : External parts, such as the anti-oscillation part, may become necessary depending on the set condition.
Check their necessity for each set.
Page 24
TENTATIVE 2
4. Maximum Ratings at Ta = 25℃℃℃℃
Parameter Symbol Conditions Ratings Unit
Maximum supply Voltage Vcc max 1 No signal, t=1 minute 26 V
Vcc max 2 During operations 18 V
Maximum output current Io peak Per channel 4.5/ch A
Allowable Power dissipation Pd max With an infinity heat sink 50 W
Operating temperature Topr -40 to 85 ℃
Storage temperature Tstg -40 to 150 ℃
Thermal resistance between the junction and case
5. Recommended operating range at Ta=25℃℃℃℃
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage Vcc 14.4 V
Recommended load resistance RL op 4 Ω
Operating supply voltage range Vcc op A range not exceeding Pdmax 9 to 16 V
6. Electrical Characteristics at Ta=25℃℃℃℃, Vcc=14.4V, RL=4Ω, f=1kHz, Rg=600Ω
Parameter Symbol
Quiescent current Icco RL=∞, Rg=0Ω 200 400 mA
Standby current Ist Vst=0V 10 uA
Voltage gain VG Vo=0dBm 25 26 27 dB
Voltage gain difference ∆VG -1 +1 dB
Output power Po THD=10% 23 28 W
Pomax1 JEITA max 43 W
Pomax2 Vcc=15.2,JEITA max 48 W
θj-c 1 ℃/W
Conditions min typ max Unit
Output offset voltage Vn offset Rg=0Ω -100 +100 mV
Total harmonic distortion THD Po=4W 0.03 0.2 %
Channel separation CHsep Vo=0dBm, Rg=10kΩ 55 65 dB
Ripple rejection ratio SVRR Rg=0Ω, fr=100Hz , Vccr=0dBm 45 65 dB
Output noise voltage VNO Rg=0Ω, B.P.F.=20Hz to 20kHz 80 200 uVrms
Input resistance Ri 40 50 65 kΩ
Mute attenuation Matt Vo=20dBm ,MUTE : ON 75 90 dB
Vstby H AMP : ON 2.5 Vcc V Standby Pin
Control voltage
Control voltage
Output offset detection
Detection threshold voltage Vosdet ±1.2 ±1.8 ±2.4 V
Note : 0dBm = 0.775Vrms
Vstby L
Vmute H MUTE : OFF OPEN - Mute Pin
Vmute L
AMP : OFF 0.0 0.5 V
MUTE : ON 0.0 1.5 V
Note : Information in this document is subject to change without notice.
Page 25
TENTATIVE 3
7. LV47002P Test and Application circuit
a
cc
cc
cc
L
D
ile
ilter
rotective
circit
D
L
D
D
D
te
circit
te
D
Lo Level
te
L
tan
itch
rotective
circit
D
D
L
The components and constant values within the test circuit are used for confirmation of characteristics
and are not guarantees that incorrect or trouble will not occur in application equipment.
Note : Information in this document is subject to change without notice.
Page 26
TENTATIVE 4
8. Explanation for the functions
1. Standby switch function (pin 4)
Threshold voltage of the pin 4 is set by about 2VBE.
The amplifier is turned on by the applied voltage of 2.5V or more. Also, the amplifier is turned off by the applied
voltage of 0.5V or less.
2. Muting function (pin 22)
Fig1 Standby equivalent circuit
The muted state is obtained by setting pin 22 to the ground potential, enabling audio muting.
The muting function is turned on by the applied voltage of 1V or less to the resistance of 10kΩ. And the muting
function is turn off when this pin opens.
Also, the time constant of the muting function is determined by external capacitor and resistor constants.
It is concerned with a pop noise in amplifier ON/OFF and mute ON/OFF. After enough examination, please set it.
Fig2 Mute equivalent circuit
3. ACGND pin (pin 16)
The capacitor of the pin 16 must use the same capacitance value as the input capacitor.
Also, connect to the same PREGND as the input capacitor.
Note : Information in this document is subject to change without notice.
Page 27
TENTATIVE 5
4. Self-diagnosis function (pin 25)
By detecting the unusual state of the IC, the signal is output to the pin 25.
Also, by controlling the standby switch after the signal of the pin 25 is detected by the microcomputer,
the burnout of the speaker can be prevented.
1) Shorting to VCC / Shorting to ground : The pin 25 becomes the low level.
2) Load shorting : The pin 25 is alternated between the low level and the high level according to the output signal.
3) Output offset detection : when the output offset voltage exceeds the detection threshold voltage,
the pin 25 becomes the low level.
* Note: The output offset abnormality is thought of as the leakage current of the input capacitor.
In addition, the pin 25 has become the NPN open collector output (active low).
The pin 25 must be left open when this function is not used.
5. Sound Quality (low frequencies)
By varying the value of input capacitor, low-frequency characteristic can be improved.
However, it is concerned the shock noise. Please confirm in each set when the capacitance value varies.
6. Pop noise
For pop noise prevention, it is recommended to use the muting function at the same time.
- Please turn on the muting function simultaneously with power supply on when the amplifier is
turned on. Next, turn off the muting function after the output DC potential stabilization.
- When the amplifier is turn off, turn off the power supply after turning on the muting function.
. Oscillation Stability
Pay due attention on the following points because parasitic oscillation may occur due to effects of the capacity
load, board layout, etc.
(1) Capacity load
When the capacitor is to be inserted between each output pin and GND so as to prevent electric mirror noise,
select the capacitance of maximum 1500 pF. (Conditions: Our recommended board, RL = 4Ω)
(2) Board layout
- Provide the VCC capacitor of 0.1µF in the position nearest to IC.
- PREGND must be independently wired and connected to the GND point that is as stable as possible,
such as the minus pin of the 2200µF VCC capacitor.
In case of occurrence of parasitic oscillation, any one of following parts may be added as a countermeasure.
Note that the optimum capacitance must be checked for each set in the mounted state.
- Series connection of CR (0.1µF and 2.2Ω) between BTL outputs
- Series connection of CR(0.1µF and 2.2Ω) between each output pin and GND.
Note : Information in this document is subject to change without notice.
Page 28
TENTATIVE 6
250
RL=Open
200
R=0Ω
150
100
Icco (mA)
50
0
6 8 10 12 14 16 18
Icco - Vcc
Vcc (V)
14
RL=Open
R=0Ω
8
6
4
2
0
6 8 10 12 14 16 18
(V)
N
V
12
10
Vcc (V)
VN - Vcc
50
f=1kHz
RL=4Ω
40
THD=10%
30
20
Po (W)
Po - Vcc(THD=10%)
all channel is similar
10
0
8 10 12 14 16 18
Vcc (V)
10
1
THD - Po(f=1kHz)
Vcc=14.4V
RL=4Ω
f=1kHz
ch1
ch2
ch3
ch4
THD (%)
0.1
25
20
all channel is similar
15
10
Po (W)
Vcc=14.4V
RL=4Ω
5
THD=1%
0
10 100 1000 10000 100000
f (Hz)
Po - f(THD=1%)
10
1
THD - Po(f=100Hz)
Vcc=14.4V
RL=4Ω
f=100Hz
ch1
ch2
ch3
ch4
THD (%)
0.1
0.01
0.1 1 10 100
Po (W)
THD - Po(f=10kHz)
10
Vcc=14.4V
RL=4Ω
f=10kHz
1
THD (%)
0.1
0.01
0.1 1 10 100
ch1
ch2
ch3
ch4
Po (W)
0.01
0.1 1 10 100
Po (W)
THD - f
10
Vcc=14.4V
RL=4Ω
Po=4W
1
THD (%)
0.1
0.01
10 100 1000 10000 100000
ch1
ch2
ch3
ch4
f (Hz)
Note : Information in this document is subject to change without notice.
Page 29
TENTATIVE 7
1
0
all channel is similar
-1
Vcc=14.4V
-2
Response (dB)
RL=4Ω
Vo=0dBm
-3
10 100 1000 10000 100000
f (Hz)
f-Response
150
Vcc=14.4V
RL=4Ω
100
(µVrms)
NO
50
V
0
10 100 1000 10000 100000
VNO - Rg
ch1
ch2
ch3
ch4
Rg (Ω
80
60
40
Vcc=14.4V
CH.sep (dB)
RL=4Ω
20
Rg=10kΩ
Vo=0dBm
0
10 100 1000 10000 100000
CH.Sep - f(CH1→→→→)
ch1→ch2
ch1→ch3
ch1→ch4
f (Hz)
80
60
40
Vcc=14.4V
RL=4Ω
CH.sep (dB)
20
Rg=10kΩ
Vo=0dBm
0
10 100 1000 10000 100000
CH.Sep - f(CH3
→→→→
)
ch3→ch1
ch3→ch2
ch3→ch4
f (Hz)
80
60
40
Vcc=14.4V
RL=4Ω
CH.sep (dB)
20
Rg=10kΩ
Vo=0dBm
0
10 100 1000 10000 100000
CH.Sep - f(CH2→→→→)
ch2→ch1
ch2→ch3
ch2→ch4
f (Hz)
80
60
40
Vcc=14.4V
RL=4Ω
CH.sep (dB)
20
Rg=10kΩ
Vo=0dBm
0
10 100 1000 10000 100000
CH.Sep - f(CH4→→→→)
ch4→ch1
ch4→ch2
ch4→ch3
f (Hz)
80
60
40
VccR=0dBm
fR=100Hz
Rg=0Ω
SVRR (dB)
RL=4Ω
20
CVcc=0.1μF
0
8 10 12 14 16 18
SVRR - Vcc
Vcc (V)
ch1
ch2
ch3
ch4
80
60
40
SVRR (dB)
20
Vcc=14.4V
VccR=0dBm
Rg=0Ω
RL=4Ω
CVcc=0.1μF
0
10 100 1000 10000 100000
SVRR - f
fR (Hz)
Note : Information in this document is subject to change without notice.
R
ch1
ch2
ch3
ch4
Page 30
TENTATIVE 8
4
RL=4Ω
R=0Ω
3
2
Vosdet (V)
1
Offset DIAG - Vcc
Detection Level
60
f=1kHz
RL=4Ω
50
Pd=Vcc×Icc-Po×4ch
40
30
Pd (W)
20
10
Pd - Po
Vcc=14.4V
Vcc=16V
0
8 10 12 14 16 18
Vcc (V)
250
200
150
100
Vcc=14.4V
RL=Open
R=0Ω
Icco - Vst
Icco (mA)
50
0
0.0 1.0 2.0 3.0 4.0 5.0
Vst (V)
0
0.1 1 10 100
Po (W)
100
80
60
40
Mute ATT(dB)
20
0
0.0 1.0 2.0 3.0 4.0 5.0
Mute ATT - V Mute
Vcc=14.4V
RL=4Ω
Vo=20dBm
V Mute(V)
Note : Information in this document is subject to change without notice.
Page 31
Page 32
FEDD56V16160F-02
1
Semiconductor
This version: March. 2001
Previous version : January. 2001
MSM56V16160F
2-Bank ×××× 524,288-Word ×××× 16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16160F is a 2-Bank × 524,288-word × 16-bit Synchronous dynamic RAM fabricated in
Oki’s silicon-gate CMOS technology. The device operates at 3.3V. The inputs and outputs are LVTTL
compatible.
FEATURES
∙
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
∙ 2-Bank
∙
Single 3.3V power supply, ±0.3V tolerance
∙
Input : LVTTL compatible
∙
Output : LVTTL compatible
∙
Refresh : 4096 cycles/64ms
∙
Programmable data transfer mode
∙
CBR auto-refresh, Self-refresh capability
∙ Packages:
50-pin 400mil plastic TSOP (Type II) (TSOPII50-P-400-0.80-1K) (Product : MSM56V16160F-xxTS-K)
×
524,288-word × 16-bit configuration
- CAS Latency (1,2,3)
- Burst Length (1,2,4,8,Full Page)
- Data scramble (sequential, interleave)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM56V16160F-8 125MHz 9ns 6ns
MSM56V16160F-10 100MHz 9ns 9ns
Max.
Frequency
Access Time (Max.)
t
AC2
t
AC3
1/31
Page 33
FEDD56V16160F-02
1
Semiconductor
PIN CONFIGURATION (TOP VIEW)
V
1
CC
DQ1
2
DQ2
3
V
4
Q
SS
5
DQ3
DQ4
6
7
VCCQV
8
DQ5
9
DQ6
10
VSSQ
11
DQ7
12
DQ8
13
VCCQ
LDQM
14
15
WE
16
CAS
17
RAS
18
CS
A11
19
A10
20
A0
21
A1
22
A2
23
24
A3
CC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
2625V
V
SS
DQ16
DQ15
V
Q
SS
DQ14
DQ13
Q
CC
DQ12
DQ11
V
Q
SS
DQ10
DQ9
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
MSM56V16160F
50-Pin Plastic TSOP (II)
(K Type)
Pin Name Function Pin Name Function
CLK System Clock UDQM, LDQM Data Input / Output Mask
CS Chip Select DQi Data Input / Output
CKE Clock Enable V
A0–A10 Address V
CC
SS
Power Supply (3.3V)
Ground (0V)
A11 Bank Select Address VCCQ Data Output Power Supply (3.3V)
RAS Row Address Strobe VSSQ Data Output Ground (0V)
CAS Column Address Strobe NC No Connection
WE Write Enable
Note : The same power supply voltage must be provided to every VCC pin and VCCQ pin.
The same GND voltage level must be provided to every V
pin and VSSQ pin.
SS
2/31
Page 34
FEDD56V16160F-02
1
Semiconductor
PIN DESCRIPTION
CLK Fetches all inputs at the “H” edge.
CS
CKE
Address
A11
RAS
CAS
WE
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address : RA0 – RA10
Column Address : CA0 – CA7
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B
Functionality depends on the combination. Fo r details, see the function truth table.
MSM56V16160F
UDQM,
LDQM
DQi Data inputs/outputs are multiplexed on the same pin.
Masks the read data of two clocks lat er when UDQM and LDQM are set “H” at the “H” edg e of the
clock signal. M asks the write da ta of the sa me clock w hen UDQM and LDQM are set “H” at the “H”
edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.
3/31
Page 35
FEDD56V16160F-02
A0−A11
C
K
1
Semiconductor
BLOCK DIAGRAM
CKE
CL
CS
RAS
CAS
WE
UDQM
LDQM
Timing
Register
A11
8
8
Progra-
ming
Register
Bank
Controlle
r
Internal
Col.
Address
Counter
Column
Address
Buffers
8
Latency
& Burst
Controller
Column
Decoders
I/O
ontroller
Input
Data
Registe
r
MSM56V16160F
Input
Buffers
16 16
Sense
Amplifiers
Internal
Row
Address
Counter
Row
12
Address
Buffers
Row
Decoder
s
Row
12
Decoder
s
Word
Drivers
Word
Drivers
8Mb
Memory
Cells
8Mb
Memory
Cells
Sense
Amplifiers
Column
Decoders
16
Read
Data
Registe
r
Output
Buffers
DQ1
1616
−DQ16
4/31
Page 36
FEDD56V16160F-02
1
Semiconductor
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on Any Pin Relative to V
SS
VCC Supply Voltage V
Storage Temperature T
Power Dissipation P
Short Circuit Output Current I
Operating Temperature T
RECOMMENDED OPERATIING CONDITIONS
VIN, V
*: Ta = 25°C
MSM56V16160F
OUT
, VCCQ –0.5 to 4.6 V
CC
stg
D*
OS
opr
–0.5 to VCC+ 0.5 V
–55 to 150 °C
600 mW
50 mA
-20 to 85 °C
(Voltages referenced to VSS = 0V)
Parameter Symbol Min. Typ. Max. Unit
Power Supply Voltage VCC, VCCQ 3.0 3.3 3.6 V
Input High Voltage V
Input Low Voltag e V
IH
IL
2.0 VCC + 0.2 V
−0.3 0.8 V
PIN CAPACITANCE
(V
= 1.4V, Ta = 25°C, f = 1 MHz)
BIAS
Parameter Symbol Min. Max. Unit
Input Capacitance (CLK) C
Input Capacitance (CKE, A0 – A11, CS,
RAS, CAS, WE, UDQM, LDQM )
Input/Output Capacitance (DQ1 – DQ16) C
CLK
C
OUT
IN
2.5 4 pF
2.5 5 pF
46.5pF
5/31
Page 37
FEDD56V16160F-02
1
Semiconductor
DC CHARACTERISTICS
Parameter
Output High
Voltage
Output Low
Voltage
Input Leakage
Current
Output Leakage
Current
Average Power
Supply Current
(Operating)
Power Supply
Current
(Standby)
Average Power
Supply Current
(Clock
Suspension)
Average Power
Supply Current
(Active Standby)
Power Supply
Current (Burst)
Symbol
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC1D
I
CC2
I
CC3S
I
CC3
I
CC4
One Bank
Active
Both
Banks
Active
Both
Banks
Precharge
Both
Banks
Active
One Bank
Active
Both
Banks
Active
MSM56V16160F
Condition
Bank CKE Others
I
I
OH
OL
=2.0mA
=−2.0mA
Min. Max. Min. Max.
−10 10 −10 10 µA
−10 10 −10 10 µA
tCC = Min.
CKE≥V
IH
tRC = Min.
No Burst
tCC = Min.
CKE≥V
IH
tRC = Min.
t
= Min.
RRD
No Burst
CKE≥VIHtCC = Min. 35 30 mA 3
CKE≤V
CKE≥V
CKE≥V
tCC = Min. 3 3mA2
IL
tCC = Min. 40 35 mA 3
IH
tCC = Min. 125 100 mA 1,2
IH
MSM56V16160
F-8 F-10
2.4 2.4 V
0.4 0.4 V
80 70 mA 1,2
115 95 mA 1,2
Unit Note
Power Supply
Current
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
Average Power
Supply Current
(Power Down)
I
CC5
I
CC6
I
CC7
One Bank
Active
Both
Banks
Precharge
Both
Banks
Precharge
CKE≥V
CKE≤VILtCC = Min. 2 2mA
CKE≤V
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
tCC = Min.
IH
tRC = Min.
tCC = Min. 2 2mA
IL
80 70 mA 2
6/31
Page 38
FEDD56V16160F-02
1
Semiconductor
MSM56V16160F
Mode Set Address Keys
CAS Latency Burst Type Burst Length
A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1
0 0 0 Reserved 0 Sequential 0 0 0 1 1
001 1 1Interleave001 2 2
010 2 010 4 4
011 3 011 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Full Page Reserved
Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle.
MSM56V16160F support two methods of Power on Sequence.
POWER ON SEQUENCE 1
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V
voltage has reached the specified level, pause for 200µs or more with the input kept in
CC
NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
POWER ON SEQUENCE 2
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V
voltage has reached the specified level, pause for 200µs or more with the input kept in
CC
NOP state.
3. Issue the precharge all bank command.
4. Enter the mode register setting command.
5. Apply a CBR auto-refresh eight or more times.
7/31
Page 39
FEDD56V16160F-02
1
Semiconductor
AC CHARACTERISTICS (1/2)
Parameter Symbol
CL = 3
CL = 2
CL = 1
CL = 3
Access Time from
Clock
CL = 2
CL = 1
Clock High Pulse Time
Clock Low Pulse Time
Input Setup Time
Input Hold Time
Output Low Impedance Time
from Clock
t
CC3
t
CC2
t
CC1
t
AC3
t
AC2
t
AC1
t
CH
t
t
t
t
OLZ
CL
SI
HI
MSM56V16160
F-8 F-10
Min. Max. Min. Max.
8 10
12 15
24 30
6 9
9 9
22 27
3 3
3 3
2 3
1 1
3 3
MSM56V16160F
Note 1,2
Unit Note
ns
nsClock Cycle Time
ns
ns 3,4
ns 3,4
ns 3,4
ns 4
ns 4
ns
ns
ns
Output High Impedance Time
from Clock
t
Output Hold from Clock
Random Read or Write Cycle Time t
RAS Precharge Time t
RAS Pulse Width t
RAS to CAS Delay Time t
Write Recovery Time t
RAS to RAS Bank Active Delay
Time
Refresh Time t
Power-down Exit setup Time t
Input Level Transition Time t
CAS to CAS Delay Time (Min.) l
Clock Disable Time from CKE l
Data Output High Impedance Time
from UDQM, LDQM
t
l
OHZ
t
OH
RC
RP
RAS
RCD
WR
RRD
REF
RDEtSI
T
CCD
CKE
DOZ
8 8
3 3
70 90
20 30
48 100,000 60 100,000 ns
20 30 ns
8 15 ns
20 20 ns
64 64 ms
+1CLK tSI +1CLK ns
3 3ns
11Cycle
11Cycle
22Cycle
ns
ns 3
ns
ns
Dada Input Mask Time from UDQM ,
LDQM
l
DOD
00Cycle
8/31
Page 40
FEDD56V16160F-02
1
Semiconductor
AC CHARACTERISTICS (2/2)
Parameter Symbol
Data Input Mask Time from Write
Command
Data Output High Impedance Time
from Precharge Command
l
DWD
l
ROH
Active Command Input Time from
Mode Register Set Command Input
l
MRD
(Min.)
Write Command Input Time from
Output
l
OWD
Notes: 1. AC measurements assume that t
MSM56V16160
F-8 F-10
Min. Max. Min. Max.
00Cycle
CL CL Cycle
22Cycle
22Cycle
= 1ns.
T
MSM56V16160F
Note 1,2
Unit Note
2. The reference level for timing of input signals is 1.4V.
3. Output load.
Z=50Ω
Output
4. The access time is defined at 1.4V.
5. If t
is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.
T
50pF (External Load)
9/31
Page 41
FEDD56V16160F-02
C
R
C
W
1
Semiconductor
TIMING CHART
Read & Write Cycle (Same Bank) @CAS
CLK
CKE
S
AS
t
RCD
AS
CAS Latency====2, Burst Length====4
CASCAS
t
RC
MSM56V16160F
t
RP
ADDR
A11
A10
DQ
E
UDQM,
Ra Ca0
Row Active
t
OH
Qa1
Qa0
t
AC
Read Command Precharge Command
Qa2
t
Qa3
OHZ
RbRa
Row Active
Cb0Rb
Db0 Db1 Db2 Db3
t
WR
Write Command Precharge Command
10/31
Page 42
FEDD56V16160F-02
C
R
C
W
Q
1
Single Bit Read-Write-Read Cycle (Same Page) @CAS
Semiconductor
CAS Latency====2, Burst Length=4
CASCAS
t
CH
CLK
t
CC
t
CL
High
CKE
S
t
HI
t
SI
AS
I
t
t
SI
HI
CCD
AS
t
SI
t
SI
ADDR
t
SI
Ra CcCbCa
MSM56V16160F
A11
A10
DQ
E
UDQM,
M
LD
t
HI
BS BS BSBSBS
Ra
Row Active
t
AC
t
OLZ
t
Read Command
t
OHZ
Qa
OH
l
OWD
Write Command
t
HI
t
HI
Db
t
SI
t
HI
t
SI
Read Command
Qc
Precharge Command
11/31
Page 43
FEDD56V16160F-02
1
Semiconductor
MSM56V16160F
*Note: 1. When CS is set “High” at a clock transition from “Low” to “High ”, all inputs except CKE, UDQM
and LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A11.
A11 Active, read or write
0 Bank A
1 Bank B
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10 A11 Operation
0 0 After the end of burst, bank A holds the idle status.
1 0 After the end of burst, bank A is precharged automatically.
0 1 After the end of burst, bank B holds the idle status.
1 1 After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be prechar ged is s elected by the A10 an d A 1 1 inpu ts.
A10 A11 Operation
0 0 Bank A is precharged.
0 1 Bank B is precharged.
1 X Both banks A and B are precharged.
5. The input data and the write command are latched by the same clock (Write latency=0).
6. The output is forced to high impedance by (1CLK+ t
) after UDQM, LDQM entry.
OHZ
12/31
Page 44
FEDD56V16160F-02
C
RASC
W
1
Page Read & Write Cycle (Same Bank) @CAS
Semiconductor
CAS Latency====2, Burst Length=4
CASCAS
CLK
CKE
S
Bank A Active
AS
I
CCD
ADDR
MSM56V16160F
High
Cc0 Cd0Ca0 Cb0
A11
A10
DQ
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0
l
OWD
t
WR
Note 2
∗
E
Note 1
∗
UDQM,
LDQM
Read Command
Read Command
Write Command
Write Command
Precharge Command
*Note: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the
write command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait t
after the last write data input.
WR
Input data during the precharge input cycle will be masked internally.
13/31
Page 45
FEDD56V16160F-02
CS R
C
W
A
C
C
C
1
Semiconductor
Read & Write Cycle with Auto Precharge @ Burst Length====4
CLK
CKE
AS
AS
ADDR
Ra
t
RRD
Rb
Ca
High
Cb
MSM56V16160F
A11
A10
E
AS Latency=1
DQ
UDQM,
LDQM
AS Latency=2
DQ
UDQM,
LDQM
AS Latency=3
DQ
Ra
Rb
Qa0
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
A-Bank Precharge Start
Qa1 Qa2 Qa3
-Bank Precharge Start
Qa0
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3 Qa0
UDQM,
LDQM
Row Active
(A-Bank)
Row Active
(B-Bank)
A Bank Read with
Auto Precharge
t
-
B Bank Write with
Auto Precharge
WR
B Bank Precharge
Start Point
14/31
Page 46
FEDD56V16160F-02
C
R
C
W
1
Semiconductor
Bank Interleave Random Row Read Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
S
AS
AS
ADDR
RAa
tRC
t
RRD
CAa
RBb CBb RAc CAc
High
MSM56V16160F
A11
A10
DQ
E
UDQM,
LDQM
RAa
Row Active
(A-Bank)
Read Command
(A-Bank)
RBb RAc
QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3
Row Active
(B-Bank)
Precharge Command
(A-Bank)
Read Command
(B-Bank)
Row Active
(A-Bank)
Read Command
(A-Bank)
Precharge Command
(B-Bank)
15/31
Page 47
FEDD56V16160F-02
C
R
C
W
1
Semiconductor
Bank Interleave Random Row Write Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
S
AS
AS
ADDR
RAa
CAa
RBb CBb RAc CAc
High
MSM56V16160F
A11
A10
DQ
E
UDQM,
LDQM
RAa
Row Active
(A-Bank)
RBb RAc
DAa0 DAa1 DAa2 DAa3
Row Active
(B-Bank)
Write Command
(A-Bank)
DBb0 DBb1 DBb2 DBb3 DAc0 DAc1
Precharge Command
(A-Bank)
Precharge Command
Write Command
(B-Bank)
Row Active
(A-Bank)
Write Command
(A-Bank)
(B-Bank)
Precharge Command
(A-Bank)
16/31
Page 48
FEDD56V16160F-02
CS R
C
W
1
Semiconductor
Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4
CLK
CKE
High
∗Note 1
AS
AS
ADDR
RAa
CAa
RBb CBb CAc CBd CAe
A11
A10
RAa
RBb
DQ
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
E
UDQM,
LDQM
Row Active
(A-Bank)
Read Command
(A-Bank)
Row Active
(B-Bank)
Read Command
(B-Bank)
Read Command
(B-Bank)
Read Command
(A-Bank)
*Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle.
MSM56V16160F
Precharge Command
Read Command
(A-Bank)
I
ROH
(A-Bank)
17/31
Page 49
FEDD56V16160F-02
C
R
C
W
1
Bank Interleave Page Write Cycle @CAS
Semiconductor
CAS Latency=2, Burst Length====4
CASCAS
CLK
CKE
S
AS
AS
ADDR
RAa CAa
RBb CBd
MSM56V16160F
High
CAcCBb
A11
A10
DQ
E
UDQM,
LDQM
RAa RBb
Row Active
(A-Bank)
Write Command
(A-Bank)
DAa2DAa1DAa0
DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
Row Active
(B-Bank)
Write Command
(B-Bank)
Write Command
Write Command
(A-Bank)
(B-Bank)
Precharge Command
(Both Bank)
18/31
Page 50
FEDD56V16160F-02
CSR
C
W
1
Bank Interleave Random Row Read/Write Cycle @CAS
Semiconductor
CAS Latency=2, Burst Leng th=4
CASCAS
CLK
High
CKE
AS
AS
ADDR
RAa CAa RBb CBb RAc CAc
MSM56V16160F
A11
A10
DQ
E
UDQM,
LDQM
RAa RBb RAc
QAa0 QAa 1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Row Active
(A-Bank)
Read Command
(A-Bank)
Row Active
(B-Bank)
Precharge Command
Write Command
(B-Bank)
(A-Bank)
Read Command
(A-Bank)
Row Active
(A-Bank)
19/31
Page 51
FEDD56V16160F-02
C
RASC
W
1
Bank Interleave Page Read/Write Cycle @CAS
CLK
CKE
ADDR
Semiconductor
S
AS
CAS Latency=2, Burst Length=4
CASCAS
CAa0 CBb0 CAc0
MSM56V16160F
High
A11
A10
DQ
E
UDQM,
Read Command
(A-Bank)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3 QAc0 QAc1
Write Command
(B-Bank)
Read Command
(A-Bank)
QAc2 QAc3
20/31
Page 52
FEDD56V16160F-02
C
RASC
W
1
Clock Suspension & DQM Operat ion Cycle @CAS
Semiconductor
CAS Latency=2, Burst Length=4
CASCAS
CLK
Note 1
∗
CKE
S
AS
ADDR
Ra Ca Cb Cc
MSM56V16160F
Note 1
∗
A11
A10
DQ
Ra
Qa0 Qa1 Qa2 Qb0 Qb1 Dc0
Note 2
∗
t
t
OHZ
E
UDQM,
LDQM
Row Active
Read Command
CLOCK
Suspension
Read DQM
Read Command
Read DQM
*Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When UDQM and LDQM are asserted, the read data after two clock cycles is masked.
3. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the i nput/output data of DQ1 – DQ8 is masked.
5. When UDQM is set High, the input/output data of DQ9 – DQ16 is masked.
∗
Write
Command
Dc2
Note 3
Write
DQM
CLOCK Suspension
Write DQM
21/31
Page 53
FEDD56V16160F-02
CSRASC
W
1
Read to Write Cycle (Same Bank) @CAS
CLK
CKE
ADDR
Semiconductor
AS
CAS Latency=2, Burst Length=4
CASCAS
∗Note 1
t
RCD
Ra Ca0 Cb0
MSM56V16160F
A11
A10
DQ
E
UDQM,
LDQM
Row Active
*Note: 1. In Case
The minimum command interval is [burst length + 1] cycles.
UDQM, LDQM must be high at least 3 clocks prior to the write command.
Ra
Read Command
CAS
Db0 Db1
Write Command
Db2 Db3Da0
t
Precharge Command
WR
latency is 3, READ can be interrupted by WRITE.
22/31
Page 54
FEDD56V16160F-02
CSR
C
W
y
y
y
1
Semiconductor
Read Interruption by Precharge Command @Burst Length====8
CLK
CKE
AS
AS
ADDR
Ra
Ca
High
MSM56V16160F
A11
A10
E
CAS Latenc
DQ
UDQM,
LDQM
CAS Latenc
DQ
UDQM,
LDQM
CAS Latenc
DQ
=1
=2
=3
Qa0
Qa1RaQa2
Qa0 Qa1 Qa2
Qa4 Qa5
Qa3
Qa3 Qa4 Qa5
Qa0 Qa1 Qa2
∗Note 1
l
ROH
∗Note 1
l
Qa3 Qa4
ROH
∗Note 1
Qa5
l
ROH
UDQM,
LDQM
Row Active Read Command Precharge Command
*Note: 1. if row precharge is asserted before a burst read ends, then the read data will not output after l
CAS
equals
latency.
ROH
23/31
Page 55
FEDD56V16160F-02
C
R
C
W
y
y
1
Semiconductor
Burst Stop Command @Burst Length=8
CLK
CKE
S
AS
AS
ADDR
Ca
MSM56V16160F
High
Cb
A11
A10
E
CAS Latency=1
DQ
UDQM,
LDQM
CAS Latenc
DQ
UDQM,
LDQM
CAS Latenc
DQ
=2
=3
Qa0 Qa1 Qa2 Qa3 Qa4
Qa0 Qa1 Qa2 Qa3 Qa4
Qa0 Qa1 Qa2 Qa3 Qa4
Qb0 Qb1 Qb2 Qb3 Qb4
Qb0 Qb1 Qb2 Qb3 Qb4
Qb0 Qb1 Qb2 Qb3 Qb4
UDQM,
LDQM
Read Command
Burst Stop Command Write Command
Burst Stop Command
24/31
Page 56
FEDD56V16160F-02
C
R
C
W
1
Semiconductor
Power Down Mode @CAS Latency=2, B urst Length=4
CLK
∗Note 2
t
(min.)
PDE
t
SI
Ra Ca
CKE
S
AS
AS
ADDR
t
SI
∗Note 1
t
REF
MSM56V16160F
t
SI
A11
A10
DQ
Ra
Qa0 Qa1 Qa2
E
UDQM,
LDQM
Power-down
Entry
Power-down
Exit
Row
Active
Clock
Suspension
Entry
Suspension Exit
Read Command
Clock
Precharge Command
*Note: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16160F enters
power-down mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, CKE h as to be set h igh for longer than t
PDE (tSI
+ 1CLK).
25/31
Page 57
FEDD56V16160F-02
C
R
C
W
Q
1
Semiconductor
Self Refresh Cycle
CLK
CKE
t
SI
S
AS
AS
ADDR
MSM56V16160F
t
RC
Ra
A11
A10
DQ
E
UDQM,
M
LD
Hi-Z
Self Refresh Entry Self Refresh Exit
BS
Ra
Row Active
26/31
Page 58
FEDD56V16160F-02
CSR
C
W
1
Semiconductor
Mode Register Set Cycle Auto Refresh Cycle
CLK
CKE
AS
AS
ADDR
High High
l
MRD
Key Ra
MSM56V16160F
t
RC
DQ
E
UDQM,
LDQM
Hi - Z Hi - Z
MRS Auto Refresh
New Command
Auto Refresh
27/31
Page 59
FEDD56V16160F-02
1
Semiconductor
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current
1
State
Idle
Row Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS RAS CAS WE
HXXXX X NOP
LHHHX X NOP
LHHLBA X
LHLXBA CA
L L H H BA RA Row Active
L L H L BA A10
LLLHX X
LLLLLOP CodeMode Register Write
HXXXX X NOP
LHHXX X NOP
LHLHBACA, A10Read
L H L L BA CA, A10 Write
LLHHBARA
L L H L BA A10 Precharge
LLLXX XILLEGAL
H X X X X X NOP (Continue Row Active after Burst ends )
L H H H X X NOP (Continue Row Active after Bur st ends)
L H H L X X Term Burst --> Row Active
LHLHBACA, A10
L H L L BA CA, A10
LLHHBARA
L L H L BA A10 Term Burst, execute Row Prechar ge
LLLXX XILLEGAL
H X X X X X NOP (Continue Row Active after Burst ends )
L H H H X X NOP (Continue Row Active after Bur st ends)
L H H L X X Term Burst --> Row Active
LHLHBACA, A10
L H L L BA CA, A10
LLHHBARA
L L H L BA A10
LLLXX XILLEGAL
H X X X X X NOP (Continue Burst to End and enter Ro w Precharge)
L H H H X X NOP (Continue Burst to End and e nter Row Precharge)
LHHLBA X
LHLHBACA, A10
L H L L X X ILLEGAL
L L H X BA RA, A10
LLLXX XILLEGAL
H X X X X X NOP (Continue Burst to End and enter Row Precharge)
L H H H X X NOP (Continue Burst to End and enter Row Precharge)
LHHLBA X
LHLHBACA, A10
BA ADDR Action
ILLEGAL
ILLEGAL
NOP
Auto-Refresh or Self-Refresh
ILLEGAL
Term Burst, start new Burst Read
Term Burst, start new Burst Write
ILLEGAL
Term Burst, start new Burst Read
Term Burst, start new Burst Write
ILLEGAL
Term Burst, execute Row Pr echarge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
4
5
2
3
3
2
3
3
2
2
2
2
2
2
MSM56V16160F
3
28/31
Page 60
FEDD56V16160F-02
1
Semiconductor
FUNCTION TRUTH TABLE (Table 2) (2/2)
Current
1
State
Write with
Auto
Precharge
Precharge
Write
Recovery
Row Active
Refresh
Mode
Register
Access
CS RAS CAS WE
L H L L X X ILLEGAL
L L H X BA RA, A10
LLLXX XILLEGAL
HXXXX X
LHHHX X
LHHLBA X
LHLXBA CA
LLHHBARA
L L H L BA A10
LLLXX XILLEGAL
HXXXX X NOP
LHHHX X NOP
LHHLBA X
LHLXBA CA
LLHHBARA
L L H L BA A10
LLLXX XILLEGAL
HXXXX X
LHHHX X
LHHLBA X
LHLXBA CA
LLHHBARA
L L H L BA A10
LLLXX XILLEGAL
HXXXX X
LHHXX X
L H L X X X ILLEGAL
L L H X X X ILLEGAL
LLLXX XILLEGAL
HXXXX X NOP
LHHHX X NOP
L H H L X X ILLEGAL
L H L X X X ILLEGAL
L L X X X X ILLEGAL
BA ADDR Action
ILLEGAL
NOP --> Idle after t
NOP --> Idle after t
ILLEGAL
ILLEGAL
ILLEGAL
NOP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Row Active after t
NOP --> Row Active after t
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t
NOP --> Idle after t
2
2
2
2
4
2
2
2
2
2
2
2
2
ABBREVIATIONS
RA = Row Address BA = Bank Address NOP = No OPeration command
CA = Column Address AP = Auto Precharge
MSM56V16160F
RP
RP
RCD
RCD
RC
RC
∗
Notes :1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. Satisfy the timing of l
and tWR to prevent bus contention.
CCD
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
29/31
Page 61
FEDD56V16160F-02
1
Semiconductor
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State (n) CKEn-1 CKEn
Self Refresh
6
H X XXXX XINVALID
L H H X X X X Exit Self Refresh --> ABI
L H L H H H X Exit Self Refresh --> ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self Refresh)
6
Power Down
H X XXXX XINVALID
L H H X X X X Exit Power Down --> ABI
L H L H H H X Exit Power Down --> ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
LHLLXXX
L L X X X X X NOP (Continue power down mode)
7
All Banks Idle
(ABI)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H L X ILLEGAL
H L L L L H X Enter Self Refresh
H L LLLL XILLEGAL
L L XXXX XNOP
Any State Other
than Listed
Above
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend Next Cycle
L H X X X X X Enable Clock of Next Cycle
L L X X X X X Continue Clock Suspension
CS RAS CAS WE
ADDR Action
ILLEGAL
MSM56V16160F
6
*Notes :6 . If the minimum set-up t ime t
asynchronously so that a command can be input in the same internal clock cycle.
7. Power-down and self-refresh can be entered only when all the banks are in an idle state.
is satisfied when CKE transition from “L” to “H”, CKE operates
PDE
30/31
Page 62
FEDD56V16160F-02
1
Semiconductor
MSM56V16160F
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
4.
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or elect rical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
31/31
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Confidential
S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW
S5L8035Ui
CDMP3 SOC
V1.1
1-1
Page 64
Confidential
PRODUCT OVERVIEW S5L8035Ui (Preliminary Spec)
1 PRODUCT OVERVIEW
INTRODUCTION
S5L8035Ui Audio MP3CDP SoC provides a cost-effective solution for Audio CD application. The S5L8035Ui SoC
solution presents a rich set of features for a typical stand-alone Audio CD system: high-quality audio processing,
fully embedded CD front-end (RF, servo control, and CD-DSP), up to 4megabit flash memory support. S5L8035
also includes the following components: a 16-bit CPU with 24-bit audio DSP coprocessor, SDRAM, Serial-Flash,
4-channel timers, I/O ports, audio PWM processor, 1-channel UARTs with handshake, IIC-BUS interface, IIS
interface, SPI interface, PLLs for clock generation.
Ui
Especially, one newly adopted feature of S5L8035
CalmADM, a cost effective MCU+DSP solution based on Samsung’s 16-bit MCU (CalmRISC16) and Samsung’s
24-bit audio DSP (CalmMAC24). CalmADM performs both system control and high quality audio processing like
decoding of MP3 and decoding of WMA streams with additional special effects. The S5L8035
standard 65nm CMOS technology. Its low power and static design is suitable for power-sensitive applications.
Ui micro-architecture make the solution more cost effective.
Ui is fabricated in a
1-2
Page 65
Confidential
S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW
ARCHITECTURE
• 135MHz CalmADM (CalmRISC16, CalmMAC24, 4KB I-Cache, 12KB D-Cache, two stream buffers)
• Front-end controller (CD 4x compatible digital servo)
• Audio stream codec (Audio DSP: CalmMAC24)
• On-chip clock generator with PLL
• Multi Boot System (External S-Flash, Internal ROM, Internal SRAM, External SDRAM(EDO))
• Core peripherals (IIC, UART, SPI, IR, I/O, etc.)
AUDIO
Stream Codec MPEG-1/2/2.5 decoding, WMA decoding
Output channel 2-channel Audio PWM output
Sample rate 8kHz ~ 48 kHz
SYSTEM
Data input FEU: CD 4x
Peripheral interface UART, SPI, IR, RTC, I2C, Timer, GPIO
Memory 32KB Internal SRAM, 3.5Mbits Internal ROM, Serial Flash, SDRAM, EDO
PHYSICAL
Operating voltage 3.3V I/O, 1.2V core
Clock frequencies Input Frequency = 4.2336 MHz, Calm CLK = up to 135 MHz
Packaging 128-TQFP-1414
1-3
Page 66
Confidential
PRODUCT OVERVIEW S5L8035Ui (Preliminary Spec)
FEATURES
Processor Architecture
• CalmADM3 MCU+DSP solution
• CalmRISC16: 16-bit RISC architecture
• CalmMAC24: 24-bit DSP for audio applications
• Harvard cache architecture with separate 4KB
Instruction and 12KB Data cache
• Two stream buffers for efficient audio stream
access
• Up to 135MHz operating frequency
CalmRISC16
• 16-bit embedded RISC MCU core with high
performance, low power consumption and
efficient coprocessor interface
• Harvard RISC architecture
• Sixteen 16-bit general registers, Eight 6-bit
extension registers, 22-bit Program Counter
(PC)
CalmMAC24
• 24-bit high performance fixed-point DSP
coprocessor for audio signal processing
• 24x24 MAC operation in 1 cycle
• 2 multiplier accumulator registers, 4 general
accumulator registers and 8 pointer registers
I-Cache Memory
• A direct mapped I-Cache (4KB)
• 16 entries (8-words) with one valid bit per line
D-Cache Memory
• 8 entries (6-words) with one valid bit and one
dirty bit per a Mac data line
• 8 entries (4-words) with one valid bit and one
dirty bit per a Calm data line
• LRU replacement algorithm
• Write back write policy
Supported Content
• CD-DA, CD-MP3
Front-End Unit (FEU)
• Built-in CMOS AFE, digital servo and DSP
• CD 4x compatible digital servo
• Wide capture range PLL
• Built-in EFM slice
• EFM/EFM+ demodulator
• CLV feature
Audio Stream Codec
• MPEG 1/2/2.5 Layer 2/3 decoding
(8k~48kHz, 2 channels, up to 320kbps)
• WMA V4, V7, V8, V9(L1, L2) decoding
• Audio Sampling Frequency: 8~48KHz for
MP3 application
Audio In/Output
• Two channels audio PWM processor used as
audio DAC.
• 2 way set-associative data caches (X and Y-
Caches, 6KB each)
1-4
Page 67
Confidential
S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW
FEATURES (CONTINUED)
Memory Controller
• Supports 16-bit or 8-bit data bus width for 16M
SDRAM interface. (up to 128Mbits)
• SDRAM Interface Supports four bank, 8-bit or
16-bit data, burst(up to 16burst) mode SDRAM.
• Supports Serial-Flash interface
• Supports 4-bit or 8-bit or 16bit data bus width for
EDO interface. (up to 64Mbits)
• Supports 3.5Mbit Internal ROM interface
• Supports 32KB Internal SRAM interface
• Fully Programmable access cycles for all
memories.
Clock & Power Manager
• Low power consumption
• On-chip PLLs
• Clock can be fed selectively to each function
block by software.
• Power mode: Normal, Slow, Idle, stop, power
down mode.
• Normal mode: normal operating mode.
• Slow mode: Low frequency clock without PLL.
• Idle mode: Stop CPU clock only
• Stop mode: Stop all clock
• Power down mode: Power off chip
• Wake up by interrupt from Idle mode.
• Wake up by external interrupt from Stop mode.
• Wake up by external Host or Key from Power
down mode.
• S/W Reset by MCU for Peripheral module reset.
Interrupt Controller
• 32 interrupt sources
(Watch dog timer, 4 Timers, UART, 4 External
interrupts, IIC, IIS, SPI, IR …)
Timers
• 16-bit timer 1, 2
– Interval, free run, one shot and capture mode
– Programmable duty cycle, frequency and
polarity.
• 16-bit timer 3, 4
– Interval mode and free run mode
– Supports external clock source.
• 32-bit SCR timer
General Purpose Input/Output Ports
• 1 external interrupt port(extension possible to 4
ports)
• Up to 36 multiplexed input/output ports
IIC-BUS Interface
• 1-channel multi-master IIC-Bus.
• Serial, 8-bit oriented and bi-directional data
transfers can be made at up to 100 Kbit/s
(standard mode) or up to 400 Kbit/s (fast mode)
UART
• channel UART with DMA-based or interrupt-
based operation
• Supports 5, 6, 7 or 8-bit serial data
transmit/receive
• Supports H/W handshaking during
transmit/receive
• Programmable baud rate
Loop back mode for testing
•
• Internal 16-byte Tx FIFO and 16-byte Rx FIFO
• Max 1.5Mbps burst transmit/receive rate used by
IODMA
• Edge detect mode on external interrupt source.
• Programmable polarity of rising and falling.
• Supports FIQ (Fast Interrupt request) for very
urgent interrupt request.
1-5
Page 68
Confidential
S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW
FEATURES (CONTINUED)
USB1.1 Host Interface
• Open HCI Rev1.0 compatible
• No Bi-directional or Tri-state Buses
• No level sensitive Latches
• Support of SMI (System Management Interrupt)
• Hooks for Legacy device support
SD/MMC Interface
• Supports Multimedia card specification version
4.0 and previous version
• Supports SD Memory card specification
version1.0
• Supports SDIO card specification version 1.1
• 64bytes FIFO for data Transmit (dapth16)
• 32bytes FIFO for data Recive (dapth8)
• CRCT, Generator/Checker
• Normal, and DMA data Transfer Mode
• Support for Block and Multi-block data Read and
Write
MSTICK Interface
• Support Memory Stick
Serial Peripheral Interface (SPI)
• SPI protocol compatible
• Polling, Interrupt, DMA transfer mode
IR Input
• Supports consumer electronic IR protocol.
Frequency Counter
• Supports FM/AM Frequency Counter
Oscillator
• Single 4.2336 MHz crystal clock input.
• Oscillation Sources & PLL
Operating Voltage
• Core: 1.2 V
• I/O: 3.3V
Operating Temperature
• -40°C ~ 85°C
Operating Frequency
• CalmADM CLK : Up to 135 MHz
• System CLK : up to 125 MHz
Package
• 128-TQFP
• Max 20Mbps burst transmit/receive rate used by
IODMA.
RTC
• Supports Real Time Clock
Watchdog Timer
• 11-bit Watchdog Timer.
• Interrupt request or system reset at time-out.
1-1
Page 69
Confidential
S5L8035Ui (PRELIMINARY SPEC) PRODUCT OVERVIEW
Figure 1-2. S5L8035
1-7
Ui 128 Pin Assignments
Page 70
Confidential
S5L8035Ui (Preliminary Spec) ELECTRICAL DATA
2 ELECTRICAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 29-1. Absolute Maximum Rating
Symbol Parameter Rating Unit
VDD
V
DDP
VIN
V
OUT
I
latch
T
STG
1.2V core DC supply voltage 1.3 V
3.3V I/O DC supply voltage 3.8 V
DC input voltage 3.3 V input buffer 3.8
DC output voltage 3.3 V output buffer 3.8
Latch-up current Imon +100, -100 mA
Storage temperature – 65 to 150
V
V
o
C
RECOMMENDED OPERATING CONDITIONS
Table 29-2. Recommended Operating Conditions
Symbol Parameters Condition Min Type Max Unit
VDD
V
DDP
VIN
V
OUT
T
OPR
IDD
1.2V core DC supply voltage Commercial & industrial 1.1 1.2 1.3 V
3.3V I/O DC supply voltage Commercial & Industrial 3.0 3.3 3.6 V
DC input voltage 3.3V input buffer 3.0 3.3 3.6 V
DC output voltage 3.3V output buffer 3.0 3.3 3.6 V
Operating temperature Industrial -40 85
Normal operating current (System CLK = 120 MHz) mA
1.2V core supply current
3.3V I/O supply current
Calm CLK = 135MHz, VDD =
1.35V
Calm CLK = 135MHz, V
3.6V
DDP
=
– – –
– – –
o
C
29-1
Page 71
Confidential
ELETRICALL DATA S5L8035Ui (Preliminary Spec)
D.C. ELECTRICAL CHARACTERISTICS
Table 29-3. Normal I/O PAD D.C. Electrical Characteristics
(V
= 1.65V~3.60V, T
DD
Symbol Condition Min Typ Max Unit
High Level Input Voltage
VIL
Low Level Input Voltage
VIH
LVCMOS
Interface
LVCMOS
Interface
= industrial -40 to 85 ℃)
OPR
0.7VDD VDD+0.3 V
-0.3 0.3VDD V
∆V
IIH
IIL
VOH I
VOH I
Hysteresis
Voltage
High Level Input Current
Input Buffer Vin=VDD -10 10 uA
Input Buffer with
pull-down
Low Level Input Current
Input Buffer Vin=VSS -10 10 uA
Input Buffer with
pull-up
Vin=VDD
Vin=VSS
0.1VDD V
VDD=3.3V 20 70 130
VDD=2.5V 10 40 80
VDD=1.8V 5 20 40
VDD=3.3V -130 -70 -20
VDD=2.5V -80 -40 -10
VDD=1.8V -40 -20 -5
=100uA VDD-0.2 V
OH
=100uA 0.2 V
OL
uA
uA
IOZ
CIN
C
OUT
29-2
Tri-State Output
Leakage Current
capacitance
capacitance
Input
Output
Vout=VSS or VDD -10 10 uA
Any input and
Bidirectional buffers
Any output buffer 5 pF
5 pF
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