For servicing CDR779, the set can be devided into three parts
1. The display board (partly) 1002, the I/O board 1004, the
headphone board (partly) 1002, the IR board (partly) 1002, the
ON/OFF & Standby LED board (partly) 1002 and the CD-out
board (partly) 1002 have to be repaired at component level. The
power supply unit 1003 is available as spare part, but can also be
repaired at component level.
2. The CDR module (containing the CDR loader 81, CDR main
board 1001 and loader bracket 82, 83) can also be repaired at
component level with the help of COMPAIR release 1.6 and
higher. With this tool the diagnosing of the set can be done in an
interactive way. In the tool also the adjustment procedure has
been implemented. This is absolutely necessary in case the CDR
mainboard and/or (CDR loader) CDM is disconnected from the
matched production combination. Only designated workshops
can perform these repairs. Please send the complete set to the
designated workshop.
3. The CD module (containing the CD loader 131, CD mainboard
1005 and loader bracket 132) is a new module with VAL1250
loader assy but also a separate CDM and separate loader parts
will be available via service stock. The CD mainboard can be
repaired at component level.
Also available : Circuit Description “The Basics of Compact Disc
Recordable/Rewriteable”. Service codenumber 4822 725 25242.
Second line Repairmanual . Service codenumber 3104 125 40110.
Copyright 2000 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
ContentsPage
1. Technical Specifications2
2. Warning and Servicing Hints4
3. User Instructions7
Mechanical Instructions
4.
Wiring Diagram CDR19
Wiring Diagram CD loader20
Exploded View CDR21
Exploded View CD loader22
Dismantling Instructions23
Block diagram, Circuit diagrams and PWB’sDiagram PWB
Number and height of feet: 4x11mm foiled
Apparatus tray closed (WxDxH): 435x305x75mm
(without feet)
Weight without packaging: 3.2kg
Weight with packaging: 4.2kg
Technical Specifications CDR779
GB 3CDR7791.
Page 4
GB 4CDR7792.
Warnings and Servicing Hints
2.Warnings and Servicing Hints
GB
WARNING
All ICs and many other semi-conductors are
susceptible to electrostatic discharges (ESD).
Careless handling during repair can reduce
life drastically.
When repairing, make sure that you are
connected with the same potential as the
mass of the set via a wrist wrap with
resistance.
Keep components and tools also at this
potential.
F
ATTENTION
Tous les IC et beaucoup d'autres semiconducteurs sont sensibles aux décharges
statiques (ESD).
Leur longévité pourrait être considérablement
écourtée par le fait qu'aucune précaution
n'est prise a leur manipulation.
Lors de réparations, s'assurer de bien être
relié au même potentiel que la masse de
l'appareil et enfiler le bracelet serti d'une
résistance de sécurité.
Veiller a ce que les composants ainsi que les
outils que l'on utilise soient également a ce
potentiel.
D
Alle IC und viele andere Halbleiter sind
empfindlich gegen elektrostatische
Entladungen (ESD).
Unsorgfältige Behandlung bei der Reparatur
kann die Lebensdauer drastisch vermindern.
Sorgen sie dafür, das Sie im Reparaturfall
über ein Pulsarmband mit Widerstand mit
dem Massepotential des Gerätes verbunden
sind.
Halten Sie Bauteile und Hilfsmittel ebenfalls
auf diesem Potential.
GB
Safety regulations require that the set be restored to its original condition
and that parts which are identical with those specified be used.
NL
Veiligheidsbepalingen vereisen, dat het apparaat in zijn oorspronkelijke
toestand wordt terug gebracht en dat onderdelen, identiek aan de
gespecifieerde worden toegepast.
F
Les normes de sécurité exigent que l'appareil soit remis a l'état d'origine et
que soient utilisées les pièces de rechange identiques à celles spécifiées.
WARNUNG
NL
Alle IC's en vele andere halfgeleiders zijn
gevoelig voor elektrostatische ontladingen
(ESD).
Onzorgvuldig behandelen tijdens reparatie
kan de levensduur drastisch doen
verminderen.
Zorg ervoor dat u tijdens reparatie via een
polsband met weerstand verbonden bent met
hetzelfde potentiaal als de massa van het
apparaat.
Houd componenten en hulpmiddelen ook op
ditzelfde potentiaal.
Tutti IC e parecchi semi-conduttori sono
sensibili alle scariche statiche (ESD).
La loro longevita potrebbe essere fortemente
ridatta in caso di non osservazione della piu
grande cauzione alla loro manipolazione.
Durante le riparazioni occorre quindi essere
collegato allo stesso potenziale che quello
della massa dell'apparecchio tramite un
braccialetto a resistenza.
Assicurarsi che i componenti e anche gli
utensili con quali si lavora siano anche a
questo potenziale.
WAARSCHUWING
I
AVVERTIMENTO
D
Bei jeder Reparatur sind die geltenden Sicherheitsvorschriften zu beachten.
Der Originalzustand des Gerats darf nicht verandert werden.
Fur Reparaturen sind Original-Ersatzteile zu verwenden.
I
Le norme di sicurezza esigono che l'apparecchio venga rimesso nelle
condizioni originali e che siano utilizzati pezzi di ricambiago idetici a quelli
specificati.
SHOCK, FIRE HAZARD SERVICE TEST:
CAUTION: After servicing this appliance and prior to returning to customer, measure the resistance between
either primary AC cord connector pins (with unit NOT connected to AC mains and its Power switch ON), and the
face or Front Panel of product and controls and chassis bottom,
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC
power is applied, and verified before return to user/customer.
Ref.UL Standard NO.1492.
NOTE ON SAFETY:
Symbol
: Fire or electrical shock hazard. Only original parts should be used to replace any part with symbol
Any other component substitution(other than original type), may increase risk or fire or electrical shock hazard.
“Pour votre sécurité, ces documents
doivent être utilisés par des
spécialistes agrées, seuls habilités à
réparer votre appareil en panne.”
CL 96532086_021.eps
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Page 5
Warnings and Servicing Hints
SERVICING HINTS
In the set, chip components have been applied. For disassembly and assembly check the figure below.
GB 5CDR7792.
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Page 6
GB 6CDR7792.
Warnings and Servicing Hints
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Page 7
3.Directions for use
English
9
1 Connection to mains
2 ANALOG OUT ............connects CD player deck to the
line input of an amplifier (left and
right)
3 DIGITAL OUT CD ......connects CD player deck to the
digital coaxial input of e.g.
amplifier or recording device
4 ANALOG IN ................connects to the line output of an
amplifier (left and right)
5 ANALOG OUT CDR & CD
......................................connects to the line input of an
amplifier (left and right)
6 DIGITAL IN..................connects to the digital coaxial
output of an external CD player
7 DIGITAL OUT CDR & CD
......................................connects to the digital coaxial
input of e.g. amplifier or recording
device
8 OPTICAL IN ................connects to the digital optical
output of an external CD player
1 REM/REC TIME ..........remaining time/remaining
recording time/recording time
2 TRACK ........................track number
3
FE
..............................balance (lights during balance
adjustment)
4 TOTAL REM
TRACK TIME ..............total or remaining time of disc or
track
5
}
................................remote control active
6 STEP ............................indicates the number of tracks in a
program
7 Track bar ....................indicates:
- tracks on a disc or in a program
- track in play
8 + 20 ..............................disc or program contains more
than 20 tracks
9 PROG(ram) ..................flashes during programming/lights
in program mode
0 REPEAT TRACK/ALL..lights up when a track/ complete
disc (or program) is repeated
! SCAN ..........................lights up when the first 10
seconds of each track are played
@ SHUFFLE......................plays tracks in random order
#
s
..............................CD player deck selected
$
c
..............................CD inserted (a pre-recorded CD or
finalized CDR or CDRW disc)
% fRECORDg ............lights during recording from the
internal CD
^ L/R ; ; ........................record/play level bar. Indicates the
audio signal level
& j k ........................DJ mode selected
* iCHANGERh ........changer mode selected
( ; ..................................pause function active
) B ................................lights during play
The purpose of the dealer mode is to prevent people taking
out the CD inside the player at exhibitions, showrooms etc..
This mode disables the open/close function of the player.
The dealer mode can be switched on and off pressing keys
[OPEN/CLOSE] and [STOP] of the CDR player
simultaneously while switching on the unit. The dealer mode
is stored in the flash memory and can only be changed by
executing the above actions.
6.2Dealer diagnostics
DEALER DIAGNOSTICS
(status of player)
If power ON,
switch power OFF
Diagnostic Software
GB 45CDR7796.
Press <REWIND> + <FFWD>
simultaneously and switch
ON unit
Display blinks
“BUSY”
during test
NO
Set OK?
YES
Set displays
“
PASSED
To end test, switch OFF unit
”
Figure 6-1
Set displays
“ERROR”
CL96532086-024.eps
090999
6.2.1Description
The intention of the dealer diagnostics is to give an indication
of the CDR player status. An inexperienced, even nontechnical dealer will/can perform the test. Tests are executed
automatically without need for external tools or disassembly
of the unit. This test checks the CDR main board using the
same tests as the electrical service diagnostics program.
Only the result of the test, "PASSED" or "ERROR", will be
shown on the display. Pressing keys [F FWD] and [REWIND]
simultaneously while switching on the unit, starts the test.
Switching off the unit ends the test.
6.2.2Requirements to perform the test
•Working keyboard to start up the test.
•Working local display to check the output messages.
Page 46
GB 46CDR7796.
6.3Electrical service diagnostics
ELECTRICAL SERVICE DIAGNOSTICS
(software versions, test for defective components)
If power ON,
switch power OFF
Load CD-DA disc (SBC444A)
Press <PLAY> + <F FWD>
simultaneously and switch ON unit
PLAYER
INFORMATION
Display :
"PLAYER ID"
"SW VERSION BACK END"
"SW VERSION CDR LOADER"
(CDR775
CDR MAIN
BOARD TEST
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
"SW VERSION CD LOADER"
"DTST1"
DRAM test (7702)
"DTST2"
FLASH CHECKSUM test (7702)
"DTST3"
FLASH ERASE test (7702)
"DTST4"
CODEC test (7702)
"DTST5"
CDR LOADER
COMMUNICATION test
"DTST6"
*
CD LOADER
COMMUNICATION test
* FOR CDR775 ONLY
)
ABORT TEST
ABORT TEST
ABORT TEST
ABORT TEST
ABORT TEST
Diagnostic Software
Press <F FWD>
Press <F FWD>
Press <F FWD>
Press <F FWD>
Press <F FWD>
ABORT TEST
Press <F FWD>
ABORT TEST
Press <F FWD>
LOADER TESTS
CDR LOADER TEST
CD-DA disc must be loaded
Display shows current disc time
Test OK?
YES
CD LOADER TEST *
CD-DA disc must be loaded
Display shows current disc time
Test OK?
YES
DISPLAY TEST
DISPLAY TEST
Display segments blink at f=1kHz
KEYBOARD &
RC TEST
KEYBOARD & RC TEST
Display shows name of pressed keys
Press <F FWD>
NO
Display :
or
or
* FOR CDR775 ONLY
NO
Display :
or
or
"BERR1"
"NO CDDA"
"NO DISC"
Press <F FWD>
"BERR2"
"NO CDDA"
"NO DISC"
Press <F FWD>
Tests OK?
YES
NO
"DERRn"
Display :
n = failed test
Display next
failed test
Figure 6-2
To end test, switch OFF unit
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Page 47
Diagnostic Software
GB 47CDR7796.
6.3.1Description
The intention of the electrical service diagnostics is to show
the software versions present in the player and to direct the
dealer towards defective internal units. The units are : the
CDR main board, the CDR loader, the CD loader in case of
a CDR779 and the keyboard/display board. A sequence of
tests is executed automatically. Some of the tests can be
aborted or skipped without the result being taken into
account. External tools or disassembly of the unit is not
necessary to get the diagnostic information. Pressing keys
[PLAY/PAUSE] and [F FWD] simultaneously while switching
on the unit, starts the test. Switching off the unit ends the test.
6.3.2Requirements to perform the test
•Working keyboard to start up the test.
•Working local display to check the output messages.
•A CD-DA disc with a minimum of 3 tracks in all trays to
perform the disc test.
6.3.3Description of the tests
Player information
In this part of the test the following important information can
be checked without removing the cover :
•Recorder ID.
•SW-version back end of player.
•SW-version CDR loader.
•SW-version CD loader (only for CDR779).
CDR main board test
[F FWD] key. The message "DERRn" will be displayed with n
indicating the faulty test number.
If one of the tests is aborted with the [F FWD] key, no error
message will be displayed for this test. The flash data erase
test ("DTST3") can not be aborted !
The CDR main board test consists out of :
DRAM test
Display : "DTST1". The DRAM used for buffer management
is tested by writing, reading and verifying test patterns.
Flash checksum test
Display : "DTST2". This test checks the checksum of the
player's SW stored in the flash.
Flash data erase
Display : "DTST3". During this test, all temporary information
(CDtxt) in the flash is erased.
is performed by audio play-back of 5 seconds at the
beginning, middle and end of the disc.
CDR loader test
During the test, the current disc time is shown. In case of an
error the message "BERR1" will be displayed and the [F
FWD] key must be pressed to continue with the following
test. Pressing the [F FWD] key also aborts this test.
CD loader test
For CDR779 only. During the test, the current disc time is
shown. In case of an error the message "BERR2" will be
displayed and the [F FWD] key must be pressed to continue
with the following test. Pressing the [F FWD] key also aborts
this test.
Display test
All segments will blink at a frequency of 1 Hz. Pressing the [F
FWD] key will start the next test because the user has to
check for himself if all segments work properly.
Keyboard and remote control tests
The test will give the user the ability to test every key without
executing the function assigned to it. Therefore, the user
needs to press every key on the keyboard and the remote
control. The display will show the name of the key being
pressed. Pressing more than one key at once will give an
unpredictable result except for the service combinations :
[PLAY/PAUSE] + [STOP], [PLAY/PAUSE] + [F FWD], [F
FWD] + [REWIND], [ERASE] + [RECORD], [PLAY/PAUSE]
+ [RECORD], [OPEN/CLOSE] + [PROGRAM].
6.4Mechanical service diagnostics
MECHANICAL SERVICE DIAGNOSTICS
(test for defective components)
If power ON,
switch power OFF
Press <PLAY/PAUSE> + <STOP>
simultaneously and switch
ON unit
<
OPEN
<
CLOSE
>
>
Display shows
FOCUS TEST
Display shows
Visual inspection
SLEDGE TEST
Visual inspection
Display shows
“BUSY”
<FWD><REWIND>
“BUSY”
TRAY TEST
Visual inspection
“OPENED”
even if tray is blocked
CODEC (ADC/DAC) test
Display : "DTST4". This test checks the CODEC IC by
writing, reading and verifying test patterns. The test is not
applicable for CDR779.
CDR communication test
Display : "DTST5". The communication between the host
processor (DASP) and the CDR loader via the DSA-R-bus is
tested.
CD communication test
Display : "DTST6"). The communication between the host
processor (DASP) and the CD loader is tested. The test is
only applicable for CDR779.
Loader tests
These tests determine if the CDR loader and the CD loader
in case of a CDR779 work correctly. A CD-DA disc with a
minimum of 3 tracks needs to be inserted in both loaders. A
disc test is executed to check focus control, disc motor
control, radial control and jump grooves control. The disc test
To end test, switch OFF unit
Figure 6-3
6.4.1Description
No external tools are required to perform this test. The cover
needs to be removed because the user has to check the
movements of the tray, focus and sledge visually. Pressing
keys [PLAY/PAUSE] and [STOP] simultaneously while
switching on the unit, starts the test. Switching off the unit
ends the test. In case of a CDR779, one can check the CD
loader mechanics in the same way by pressing the above key
combination on the CD player keys.
6.4.2Requirements to perform the test
•Working keyboard to cycle through the tests and to start
up the test.
•Working local display to check the output messages.
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GB 48CDR7796.
Diagnostic Software
6.4.3Description of the tests
Focus control test
The focussing lens is continuously moving up and down. The
display reads "BUSY".
Sledge control test
After pressing [F FWD] the sledge continuously moves up
and down. Pressing [REWIND] stops the sledge at the
position it is in and the focus control test resumes. The
display reads "BUSY".
Tray control test
This test starts from within the focus control test routine.
Pressing [OPEN/CLOSE] moves the tray in or out. In the tray
open position one can initiate focus and sledge tests by
pressing [F FWD]. One has to stop these tests pressing
[REWIND] before it is possible to close the tray again.
Depending on the action the display reads "OPEN",
"OPENED", "CLOSE" or "BUSY".
6.5DC-erase service mode
DC ERASE SERVICE MODE
(erasement of complete CD-RW)
Load CD-RW disc
Press
<ERASE> + <RECORD>
simultaneously and switch
ON unit
Display shows:
ER mm:ss
“
mm
ss:remaining seconds
TOTAL
and
illuminated
Display shows:
“
when the erase function is
if DC ERASE fails
To end test, switch OFF unit
Figure 6-4
6.5.1Description
This test is initiated by pressing [ERASE] and [RECORD]
simultaneously while switching on the unit. The player will
erase a complete CD-RW disc (including PMA and ATIP lead
out area) at speed N=2. The display shows the countdown of
the remaining time required for the operation to complete.
The format is "ER mm:ss", where "mm" are the remaining
minutes and "ss" the remaining seconds. After completion
the message "PASSED" is shown, and the player has to be
switched off and on again to start up in normal operating
mode. Switching off the unit before completion of the test,
leaves the disc in an unpredictable state. In such case only a
complete DC-erase procedure can recover the CD-RW disc.
6.5.2Requirements to perform the test
•Functional CDR player.
•A CD-RW audio disc must be present in the tray.
”
:remaining minutes
REM
are also
PASSED
”
completed
ERROR
”
“
CL96532086_027.eps
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6.6Burn in mode
6.6.1Description:
The Burn In mode is an endless cycle of:
•DC-Erase to erase the CDRW disc with maximum laser
power.
•Recording a CDRW disc
•Finalising at double speed
The Burn In mode is used to test intermittent faults of the
loader.
6.6.2Requirements to perform the test:
•Working Local Keyboard: needed to start up the test.
•Working Local Display: all output messages must be
displayed on the local display.
•Analog source connected to the CDR99 player
•CDRW disc in tray
Burn in sequence
–Initialisation
The ‘Burn In’ mode is initiated by pressing the [PLAY/
PAUSE] and [RECORD] key on the local keyboard at the
same time, and then switching the POWER switch on.
–Continuous loop
The following picture shows the burn in sequence.
DC erase
error
Finalise
complete with
or without
error
Write CDRW
Finalise
Figure 6-5 Burn in sequence
Continuously do DC erase, record complete CDRW and then
finalise until the player is powered off.
When an error is detected during writing, the DC erase
procedure is called again., the disc will be DC erased and the
cycle starts again.
During the test the display shows the number of hours for
which the test is running and the number of errors detected
during the test. The display looks as follows : “HH BI RE FE”
HH : number of hours on
“BI”: burn in mode, digits
RE: number of errors
FE: number of errors
If started up with a disc other than
a CDRW disc the display shows : ”WRONG DISC”,
if no disc is inserted display : “NO DISC”.
–End of test
To exit the Burn In mode, power off the player.
Erase complete without error
Write complete without error
digits 1 and 2
3 and 4
detected during DC
erase and write
CDRW modes on
digits 7 and 8
detected during
finalise modes on
digits 10 and 11
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7.Faultfinding trees
7.1CDR-Module
NO DISC LOADED
SWITCH ON POWER
Faultfinding trees
GB 49CDR7797.
STBY LED?
YES
PRESS <DISPLAY>
DISPLAY?
YES
DISPLAY:
"INSERT DISC"
YES
NO
CHECK:
• MAINS, MAINS CABLE
• POWER SUPPLY (SEE FAULT FINDING GUIDE PSU)
⇒
WIRING
⇒
ON/OFF SWITCH
⇒
FUSES
⇒
NO
• DISPLAY (SEE FAULT FINDING GUIDE DISPLAY BOARD)
CHECK:
NO
• WIRING
• POWER SUPPLY VOLTAGES
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
VOLTAGES
⇒
WIRING
⇒
SUPPLY VOLTAGES
⇒
CLOCK SIGNAL 8MHz
⇒
CONTROL SIGNALS
⇒
KEYBOARD
⇒
STANDBY LED
⇒
ELECTRICAL SERVICE DIAGNOSTICS:
DISPLAY TEST, KEYBOARD TEST
"BERRn"
ERROR OCCURS
"DERRn"
PRESS
<OPEN/CLOSE>
TRAY?
YES
INSERT DISC
PRESS <OPEN/CLOSE>
CD-DA DISC
LOADED?
SEE CD-DA DISC
FAULT FINDING
CHECK:
• DISPLAY BOARD (SEE FAULT FINDING GUIDE DISPLAY BOARD)
⇒
NO
• MECHANICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF ERROR OCCURS
SEE CD-R DISC
FAULT FINDING
WIRING
⇒
SUPPLY VOLTAGES
⇒
CLOCK SIGNAL 8MHz
⇒
CONTROL SIGNALS
⇒
KEYBOARD
⇒
ELECTRICAL SERVICE DIAGNOSTICS:
DISPLAY TEST, KEYBOARD TEST
CD-R DISC
LOADED?
YESYES
NONO
CD-RW DISC
LOADED?
YES
SEE CD-RW DISC
FAULT FINDING
Figure 7-1
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Page 50
GB 50CDR7797.
CD-DA DISC LOADED
DISC
DETECTION &
READING?
YES
DISPLAY:
“CD”
&
T.O.C. INFO?
YES
Faultfinding trees
CHECK:
• WIRING
• POWER SUPPLY VOLTAGES
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
CHECK:
• DISC: DIRT, SCRATCHES, DAMAGED...
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
ERROR OCCURS
"DERRn"
"DERRn"
PRESS <PLAY>
ANALOG
AUDIO
OUT?
YES
DISTORTION?
NO
HEADPHONE?
YES
DIGITAL
AUDIO
OUT?
YES
CHECK:
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
⇒
FLEX CONNECTION
⇒
+5V (pin 8 conn. 1000)
⇒
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
YES
NO
NO
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
WIRING OF HEADPHONE/IR BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
KILL VOLTAGE (pin 7 conn. 1000):
-8V DURING PLAY
⇒
KILL TRANSISTORS 7006,7007,7008, 7009
PLAY AUDIO SIGNALS DISC TRACK 15:
⇒
SIGNAL OF 5.4 VPP ON PINS 1 AND 3 OF CONN.
1000
"BERRn"
"BERRn"
"BERRn"
⇒
⇒
⇒
"BERRn"
ERROR OCCURS
⇒
FLEX CONNECTION
⇒
+5V (pin 8 conn. 1000)
ERROR OCCURS
ERROR OCCURS
FLEX CONNECTION
+5V (pin 8 conn. 1000)
DIGITAL OUT TRANSFORMER 5450, IC7005
ERROR OCCURS
"DERRn"
"DERRn"
"DERRn"
"DERRn"
PLAY BACK OF CD-DA
DISCS OK
Figure 7-2
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CD-R DISC LOADED
DISC
DETECTION &
READING?
YES
DISPLAY:
“CD R”
OPC INFO?
&
YES
Faultfinding trees
CHECK:
NO
• WIRING
• POWER SUPPLY VOLTAGES
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
NO
"BERRn"
DISPLAY:
T.O.C. INFO?
YES
“CD”
&
ERROR OCCURS
"DERRn"
CHECK:
NO
• DISC: DIRT, SCRATCHES, DAMAGED...
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
GB 51CDR7797.
"DERRn"
CD-R DISC PARTIALLY
RECORDED OR EMPTY
START MANUAL
RECORDING FROM
ANALOG SOURCE
LEVEL
ADJUSTABLE?
YES
START RECORDING
FROM DIGITAL
SOURCE
DIGITAL IN?
OPTICAL IN?
YES
FINALISED CD-R DISC
LOADED
SEE CD-DA DISC
FAULT FINDING
CHECK:
AUDIO CONNECTIONS & CABLES
•
NO
• DISPLAY BOARD (SEE FAULT FINDING GUIDE DISPLAY BOARD)
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
Figure 7-3
"DERRn"
CL 96532076_018.eps
290799
Page 52
GB 52CDR7797.
CD-RW DISC LOADED
DISC
DETECTION &
READING?
YES
DISPLAY:
“CD RW”
OPC INFO?
YES
&
NO
NO
Faultfinding trees
CHECK:
• WIRING
• POWER SUPPLY VOLTAGES
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
DISPLAY:
“CD”
T.O.C. INFO?
YES
ERROR OCCURS
&
NO
"DERRn"
CHECK:
• DISC: DIRT, SCRATCHES, DAMAGED...
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
"DERRn"
CD-RW DISC PARTIALLY
RECORDED OR EMPTY
START ERASING OF LAST RECORDED TRACK
ERASING
SUCCESSFUL?
YES
SET OK
NO
FINALISED CD-RW DISC
CHECK:
• ELECTRICAL SERVICE DIAGNOSTICS:
•
LOADED
SEE CD-DA DISC
FAULT FINDING
REPLACE CDR MODULE IF
OR
"BERRn"
IF DISC CORRUPTED TRY DC ERASE
ERROR OCCURS
Figure 7-4
"DERRn"
CL 96532076_019.eps
290799
Page 53
7.2CD Module
CD MODULE
NO DISC
POWER ON
DISC
DETECTION
STARTS?
YES
DISPLAY?
YES
PRESS
<OPEN/CLOSE>
NO
NO
Faultfinding trees
• CHECK FLEX CONNECTION FROM CDR MAIN BOARD
• POWER SUPPLY
⇒ +5V, +12V AT TESTPOINTS 28 AND 27
⇒ +5V AT CONN. 1000 PINS 1 AND 3
⇒ +5V AT IC7005 PIN 14
⇒ +3V3 AT IC7000 PINS 5,17,21,57, CHECK SAFETY RESISTORS
⇒ +5V AT IC7020 PIN 25
⇒ +10V AT IC7020 PINS 26, 27, 28
⇒ +12V AT IC7021 PIN 5, CHECK SAFETY RESISTOR R3131
⇒ +12V AT IC7022 PIN 5, CHECK SAFETY RESISTOR R3154
⇒ +5V AT IC7025 PIN 16
⇒ +5V AT IC7202 PIN 38, CHECK SAFETY RESISTOR R3308
⇒ +3V3 AT IC7309 PINS 4 AND 13, CHECK SAFETY RESISTORS R3215, R3216
⇒ +12V AT IC7120 PIN 8, CHECK SAFETY RESISTOR R3263
• CLOCKS
⇒ 8.4672MHz AT TESTPOINT 7
⇒ 12MHz AT TESTPOINTS 29 AND 30
⇒ 11.2896 AT TESTPOINT 10
⇒ 2.1168MHz AT TESPOINT 20
⇒ 44.1kHz AT TESTPOINT 21
• DISPLAY
⇒ SEE FAULTFINDING GUIDE DISPLAY BOARD
• MICROPROCESSOR 7202
GB 53CDR7797.
TRAY?
YES
LOAD DISC
(CD-DA OR PARTIALLY
RECORDED CD-R/CD-RW)
PRESS <OPEN/CLOSE>
NO
TOC?
YES
SEE NEXT PAGE:
PLAYBACK
DIAGNOSTIC SOFTWARE : MECHANICAL SERVICE DIAGNOSTICS CD LOADER : TRAY TEST
NO
•
• HF PATH
• REPLACE OR REPAIR CD LOADER ASSY (CDM MECHANISM)
⇒ CHECK TRAY MOTOR VOLTAGES
⇒ MICROPROCESSOR 7202
⇒ CHECK TRAY MOTOR DRIVER IC7021
⇒ REPLACE OR REPAIR CD LOADER ASSY:
TRAY MOTOR ASSY 02, BELT 11
DIAGNOSTIC SOFTWARE : MECHANICAL SERVICE DIAGNOSTICS CD LOADER :
⇒ CHECK WIRING TO CDM
⇒ CHECK POWER DRIVERS 7021, 7022, 7020
⇒ CHECK VOLTAGES ON POWER DRIVERS (SEE CIRCUIT DIAGRAMS)
⇒ TESTPOINTS 4, 5, 6 : PULSE DENSITY MODULATED SIGNALS
⇒ TESTPOINTS 1, 2, 3, 9 : EYEPATTERN
⇒
CHECK
CDRW DISC. EYEPATTERN OF CDRW DISC WILL BE AMPLIFIED (≈ X 2.5).
EYEPATTERN OF CDDA DISC WILL BE ATTENUATED(
⇒
CHECK
⇒ TESTPOINTS 20, 21, 22: I2S
RW
S1,S2
FOCUS TEST & SLEDGE TEST
AT TESTPOINT 8 : HIGH FOR CDDA AND CDR DISC, LOW FOR
AT TESTPOINTS 25 AND 26 (SEE CIRCUIT DIAGRAMS)
DATA, WCLK, SCLK
TRAY+, TRAY-
≈ X 0.8)
CL 96532086_030.eps
080999
Figure 7-5
Page 54
GB 54CDR7797.
Faultfinding trees
CD MODULE PLAYBACK
PRESS <PLAY>
• DAC 7309
⇒ TESTPOINTS 20, 21, 22 : I2S AT INPUT OF DAC 7309
⇒ CHECK POWER SUPPLY PINS 4, 13
⇒ CHECK CLK11 AT PIN 6 : 11.2896MHz
⇒ PIN 11 : MUTE HIGH?
⇒ TESTPOINTS 23, 24 : ANALOG OUTPUT?
⇒ REPLACE DAC 7309
• OPAMP 7120
AUDIO?
YES
NO
⇒ TESTPOINTS 23, 24 : ANALOG OUTPUT?
⇒ POWER SUPPLY: PIN 8→12V
⇒ REPLACE OPAMP 7120
DISTORTION?
NO
AUDIO
CD OUT PCB?
YES
PLAYBACK CD
MODULE OK
YES
NO
• DAC 7309
• OPAMP 7120
• FLEX TO CDR MAINBOARD
• FLEX TO CD OUT BOARD
• CHECK I/O BOARD, CD OUT BOARD
Figure 7-6
CL 96532086_031.eps
080999
Page 55
8.Faultfinding Guide
Faultfinding Guide
GB 55CDR7798.
8.1Display Board
8.1.1Description of display board
General description
The display board has three major parts : the FTD
(Fluorescent Tube Display), the display controller
TMP87C874F and the keyboard. The display controller is
controlled by the DASP master processor on the CDR main
board. The communication protocol used is I2C. So all the
information between DASP and display controller goes via
the SDA or I2C DATA and SCL or I2C CLK lines.
Communication is always initiated by the DASP on the CDR
main board. Unlike the previous generations of CDR players,
the interrupt generated by the display controller at key-press
or reception of remote control is not used. Instead, the DASP
polls the display controller for these events.
BLOCK DIAGRAM
TMP87C874F
64 63 6261 6059 58 5756 55254 53
I/O PORT8 (VFT)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O PORTD (VFT)I/O PORT9 (VFT)
VKK
I/O PORT0
3
1
DATA MEMORY
TIMER/COUNTER
8 BIT A/D
CONVERT.
I/O PORT7 (VFT)
( RAM )
512X8 BIT
16 BIT
CLOCK/TIMING CONTROLLER
VSS1
RESETN
XOUT
XIN
79819
10
52
PROGR MEMORY
( ROM )
8kX8 BIT
C P U
INTERRUPT
CONTROLLER
( I/O PORT2 )
P22
P21
TEST1
P20
13
14121117 1820 2122
Display controller TMP87C874F
TMP87C874F (IC7104) is a high speed and high
performance 8-bit single chip microprocessor, containing 8bit A/D conversion inputs and a VFT (Vacuum Fluorescent
Tube) driver. In this application, its functions are :
•slave microprocessor.
•FTD driver.
•generates the square wave for the filament voltage
required for an AC FTD.
•generates the grid and segment scanning for the FTD.
•generates the scanning grid for the key matrix.
•input for remote control.
All the communication runs via the serial bus interface I2C.
The display controller uses an 8MHz resonator as clock
driver.
41
42434445464748495051
I/O PORT6 (VFT)
I/O PORT5
I/O PORT4
2
SDA
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SCK0
PROGRAM
COUNTER
TIMER/COUNTER
INT0
INT1
8 BIT
I/O PORT1
VDD
VAREF
VASS
I C
PORT3
SCL
23 244
PIN DESCRIPTIONS
INT0external interrupt input 0
INT1external interrupt input 1
RESETNreset signal input, active low
SCLI2C-bus serial clock input/output
SDAI2C-bus serial data input/output
TESTtest pin, tied to low
VAREFanalog reference voltage input
VASSanalog reference ground
VDD+5V
VKKVFT driver power supply
VSSground
XIN, XOUTresonator connecting pins for high-frequency clock
Figure 8-1
CL 96532076_028.eps
290799
Page 56
GB 56CDR7798.
Faultfinding Guide
8.1.2Test instructions
Supply voltages
The display board receives several voltages via connector
1119 (and connector 1121 for CDR570/930).
•VFTD : -38V ±5% measured at pin 2 of conn. 1119.
•VDC1-VDC2 : 3V8 ±10% measured between pin 1 and 3
of conn. 1119.
•+5V : +5V ±5% measured at pin 10 of conn. 1119 (pin 4
of conn. 1121 for CDR770).
Voltages VFTD, VDC1 and VDC2 are produced in the power
supply unit and sent to the display board via the CDR main
board. The +5V voltage is produced on the CDR main board
as D5V.
Clock signal
As clock driver for the display controller, a resonator of 8 MHz
(1110) is used. The signal can be measured at pins 8 and 9
of the display controller : 8 MHz ±5%.
Control signals
RESET
The reset signal comes via pin 4 of conn. 1119 from the
DASP master processor on the CDR main board
(SYS_RESET). The reset is low active. It should be kept low
during power up for at least 3 machine cycles with supply
voltage in operating range and a stable clock signal (1
machine cycle = 12 x 1/Fc (8 MHz) sec.). During normal
operation, the reset should be high (3V3). The high signal is
3V3 because the DASP operates on 3V3.
I2C DATA/I2C CLK
These lines connect to the DASP master processor via
respectively pin 5 and pin 7 of conn. 1119 (pin 5 of conn.
1119 and pin 1 of conn. 1121 for CDR570/930). When there
is no communication, they should have the high level (+5V).
The oscillogram below gives an indication of how these
signals should look like.
line : T7203 for G13, T7204 for G14 and T7100 for G15. A
typical grid line signal shows in the oscillogram below.
PM3392A
+4V
0V
-38V
CH1!10.0 V= MTB1.00ms ch1+
Figure 8-3 ‘Gridline’
Segment lines
Level and timing of all segment lines, P1-->P21 (P1-->P20
for CDR770), can be checked either at the FTD itself or at the
display controller. The data on these segment lines however,
depends on the characters displayed. The oscillogram below
shows a segment line with data. A segment line without data
maintains a -38V level.
PM3392A
+5V
0V
CL 96532076_024.eps
301100
PM3392A
+5V
I2C DATA
0V
+5V
I2C CLK
0V
CH1!2.00 V=
CH2 2 V= MTB10.0ms ch1+
CL 96532076_025.eps
Figure 8-2 ‘I2C signals’
FTD drive lines
Filament voltage
Should measure 3.8V ±10% (=VDC1-VDC2) between pins 12-3 and pins 45-46-47 (pins 1-2 and pins 48-49 for CDR770)
of the FTD (1113).
301100
-38V
CH1!10.0 V= MTB1.00ms ch1+
CL 96532076_027.eps
Figure 8-4 ‘Segment line’
Key matrix lines
The lines connected to pins 34, 35, 36 and 37 of the display
controller act as matrix scanners. Without a key pressed,
they maintain a low level. As soon as a key is pressed, the
scanning line connected to that key puts out a scanning
signal, which should look like the oscillogram below. This
scanning signal goes via the pressed key to I/O port 4 of the
display controller (pins 28 to 33). The display controller can
now determine which key has been pressed. Without a key
pressed, pins 28 to 33 of the display controller maintain a
high level (+5V).
301100
Grid lines
Level and timing of all grid lines, G1-->G15, can be checked
either at the FTD itself or at the display controller. Grid lines
G13, G14 and G15 each have an extra current amplifier in
Page 57
PM3392A
Faultfinding Guide
the direction of the rotation. Counting the pulses reveals the
amount of rotation. Combining and decoding this information,
the display controller will execute the appropriate task.
GB 57CDR7798.
+5V
0V
CH1!2.00 V= MTB5.00ms ch1+
CL 96532076_026.eps
Figure 8-5 ‘Key matrix scan line’
Easy jog knob
Rotary operation
The easy jog knob (1050) incorporates a whole heap of user
control possibilities in just one knob. Without the knob being
operated, pin 1 and 3 of the knob (and thus pin 16 and 17 of
the display controller), maintain the +5V level. Turning the
knob clockwise briefly connects pin 1 to GND followed by pin
3.
301100
Push button operation
This button connects to the key matrix lines and thus the
operation is identical to the ordinary keys. Without being
pressed, pin 4 of the easy jog maintains the low level, pin 5
the high level. When pressed the scanning signal goes
through the closed contact of pins 4 and 5, and can be
checked at both pins.
IR receiver - remote control
In the CDR570/930 the IR receiver TSOP1736 (6101) is
mounted on the display board. In the CDR770 that same IR
receiver (6200) is mounted on a small board together with the
headphone socket. In the CDR779 the IR receiver (6200) is
mounted on its own small board. In all versions the IR
receiver connects to the display controller. The signal coming
from the receiver can be checked at pin 22 of the display
controller. This signal is normally high (+5V). When the
remote control is being operated, pulses mixed in with the
+5V can be measured. The oscillogram gives an indication of
how the signal looks like with the RC being operated.
PM3392A
+5V
PM3392
Pin1
Pin3
CH1 5.00 V=
CH2 5.00 V= MTB20.0ms- 1.92dv ch2-
CL 96532076_023.eps
301100
Figure 8-6 ‘Turn clockwise’
Turning the knob anti-clockwise briefly connects pin 3 to
GND followed by pin 1.
PM3392
Pin1
Pin3
0V
1
CH1!2.00 V= MTB20.0ms ch1+
CL 96532076_021.eps
Figure 8-8 ‘IR receiver signal’
301100
CH1 5.00 V=
CH2 5.00 V= MTB20.0ms- 1.92dv ch2-
CL 96532076_022.eps
301100
Figure 8-7 ‘Turn anti-clockwise’
The pulses created this way arrive at pin 16 and 17 of the
display controller. The first pulse to arrive tells the controller
Page 58
GB 58CDR7798.
8.1.3Display board troubleshooting guide
SWITCH POWER ON,
EXIT STAND BY
MODE
Faultfinding Guide
CHECK :
DISPLAY?
YES
KEY
FUNCTIONS?
YES
NO
NO
• SUPPLY VOLTAGES
⇒ -38V ±5% at conn. 1119-2
⇒ 3V8 ± 10% between conn. 1119-1 and 1119-3
⇒ +5V ± 5 % at conn. 1119-10 (1121-4 for CDR570/930)
• CLOCK SIGNAL
⇒ 8Mhz at pins 8, 9 of IC7104
• CONTROL SIGNALS
⇒ RESETN 3V3 (high) at conn.1119-4 after start up
⇒ I2C DATA at conn. 1119-5
⇒ I2C CLK at conn. 1119-7 (1121-1 for CDR570/930)
• FTD DRIVE LINES
⇒ Filament voltage 3V8 ± 10% between pins 1-2-3 and
pins 45-46-47 (pins 1-2 and pins 48-49 for CDR
570/930) of the FTD (1113)
⇒ Grid lines (see test instructions)
⇒ Segment lines (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS - Local display test
CHECK:
• KEY MATRIX LINES (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS – Keyboard test
• EASY JOG KNOB (see test instructions)
REMOTE
CONTROL?
YES
DISPLAY BOARD
OK
NO
CHECK:
• IR RECEIVER signal at pin 22 of IC7104 (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS – Remote control test
Figure 8-9 ‘Display board troubleshooting’
CL 96532076_020.eps
290799
Page 59
8.2Circuit description of the current mode
power supply
8.2.1Blockdiagram
Faultfinding Guide
GB 59CDR7798.
MAINS
Lightning
Protection
EMI
FILTER
Comp
Error
Amplifier
+
-
Vfb
Verror
Rectifier
CLOCK
PWM
comparator
+
CONTROL
Start
Circuit
v
RQ
S
latch
Vcc
t2.5V
2643
Overvoltage
Protection
Output
Isense
7
9
7125
Vsense
Rsense
Vcc
+12V
6210
+5V
6230
+12V
6240
-8V
6250
VFTD
6220
VDC2
VDC1
+5V
0V
5131
2
5
7131
7201
8.2.2Function description
MOSFET 7125 is used as a power switch controlled by the
controller IC 7110. When the switch is closed, energy is
transferred from mains to the transformer. This energy is
supplied to the load when the switch is opened. Through
control of the switched-on time, the energy transferred in
each cycle is regulated so that the output voltages are
independent of load or input voltage variations. The
controlling device UC3842 is an integrated pulse width
modulator. A clock signal initiates power pulses at a fixed
frequency. The termination of each output pulse occurs when
a feedback signal of the inductor current reaches a threshold
set by the error signal. In this way the error signal actually
controls the peak inductor current on cycle-by cycle basis.
8.2.3Description of UC3842
The input voltage Vcc(pin 7) is monitored by a comparator
with hysteresis, enabling the circuit at 16V and disabling the
circuit below 10V. The error amplifier compares a voltage
Vfb(pin 2) related to the output voltage of the power supply,
with an internal 2.5V reference. The current sense
comparator compares the output of the error amplifier with
the switch current Isense(pin 3) of the power supply. The
output of the current sense comparator resets a latch, which
is set every cycle by the oscillator. The output stage is a
totem pole, capable of driving a MOSFET directly
Figure 8-10
8.2.4Start up sequence
GND
Vfb
COMP
I sense
7
VI
16V
5
4
2
1
3
REGULATION
6V
+
-
+
OSCRt/ct
2.5V
ERROR AMPI SENSE COMP
+
-
S/R
2R
R1V
2.5V
REF
-
+
5V
BIAS
CL 06532151_018.eps
S
R
LATCH
271100
1
Figure B : Blockdiagram UC3842
Figure 8-11
t1: Charging the capacitor at Vcc
C2129 wiil be charged via R3123 and R3134, C2133 and
C2111 via R3129. The output is switched off
During t1.
t2: Charging of output capacitors
When the input voltage of the IC exceeds 14,5V, the circuit is
enabled and starts to produce output pulses. The current
consumption of the circuit increases to about 17mA,
depending on the external loads of the IC. At first, the
8
Vref
6
OUTPUT
CL 06532151_019.eps
271100
Page 60
GB 60CDR7798.
Faultfinding Guide
capacitor at the Vcc pin will discharge because the primairy
auxiliary voltage, coming from winding7-9 is below the Vcc
voltage. At some moment during t2, the primary auxiliary
voltages reaches the same level as Vcc.
This primary auxiliary voltage now determines the Vcc
voltage
t3: regulation
The output voltage of the power supply is in regulation
t4: overload
When the output is shortened, the supply voltage of the
circuit will decrease and after some time drop below the
lower threshold voltage. At that moment, the output will be
disabled and the process of charging the Vcc capacitor starts
again. If the output is still shorted at the next t2 phase, the
complete start-and stop sequence will repeat. The power
supply comes in a hiccup mode.
16V
Vcc
12V
10V
Vc2134
0V
20mA
Icc
1mA
becomes reversed. This results in a current flow through the
tranformer’s secondary winding via the diodes, electrolytic
capacitors and the load. This current is also ramp shaped but
decreasing.
TimeDEAD phase : when the stored energy has been
supplied to the load, the voltage from the secondary windings
falls below the output voltage(held constant by the
electrolytic capacitors) plus the threshold voltage of the
diodes. The current in the secondary winding stops flowing.
At this point, the drain voltage of the MOSFET is not yet zero
because C2609 between drain and source contains a certain
charge. This charge will start a sine-shaped ringing together
with the transformer’s self-induction.
The oscillator will start a next cyclus which consists of the
described three phases. The time of the different phases
depends on the mains voltage and the load.
TimeDEAD is maximum at an input of 400VDC and minimum
load, it will be zero at an input of 100VDC and overload.
V2
Vosc
V1
0
Vcomp
Vsense
OUTPUT
short
Vo
0
t1
t2t3t4
Figure C : Start-up sequence
CL 06532151_020.eps
Figure 8-12
8.2.5Regulation
Figure 4 shows the most relevant signals during the
regulation phase of the power supply.
The oscillator voltage ramps up and down between V1 and
V2. The voltage at the current sense terminal is compared
every cycle with the output of the error amplifier Vcomp. The
output is switched off when the current sense level exceeds
the level at the output of the error amplifier.
TimeON phase : A drain current will flow from the positive
supply at pin 1 through the transformer’s primary winding, the
MOSFET and Rsense to ground. As the positive voltage at
pin 1 of the transformer is constant, the current will increase
linearly and create a ramp dependent on the mains voltage
and the inductance of the primary winding. A certain amount
of energy is stored in the transformer in the form of a
magnetic field. The polarity of the voltages at the secundary
windings is such that the diodes are non-conducting.
TimeDIODE phase : When the MOSFET is switched off,
energy is no longer supplied to the tranformer. The
inductance of the tranformer now tries to maintain the current
which has been flowing through it at a constant level. The
polarity of the voltage from the transformer therefore
271100
Vgate
Vdrain
Idrain
Idiodes
TonTdiode Tdead
Figure 8-13
CL 06532151_021.eps
271100
Page 61
Faultfinding Guide
GB 61CDR7798.
8.2.6Oscillograms
Oscillograms
PM3394B
ch1
1
ch3
T
ch2
3
2
ch1 : Drain voltage
ch2 : Drain current
ch3 : Gate voltage
PM3394B
ch1
ch3
1
T
CH1 2
CH2
CH3 2 V~ ALT MTB5.00us- 0.90dv ch1-
CH1 1
CH3 50mV~ ALT MTB5.00us- 0.90dv ch1-
8.2.7Circuit description
Input circuit
The input circuit consists of a lightning protection circuit and
an EMI filter.
The lightning protection comprises R3120, gasarrestor 1125
and R3124.
The EMI filter is formed by C2120, L5120, C2125 and R3124.
It prevents inflow of noise into/from the mains.
Primary rectifier/smoothing circuit
The AC input is rectified by rectifier bridge 6102 and
smoothed into C2121. The voltage over C2121 is
approximately 300V. It can vary from 100V to 390V.
Start circuit and Vcc supply
This circuit is formed by R3123, R3134, C2129, D6129,
R3129, R3111, C2133 and C2111.
When the power plug is connected to the mains voltage, the
stabilised voltage over D6129(24V) will charge C2133 via
R3129. When the voltage reaches 14,5V across C2111, the
control circuit of IC7110 is turned on and the regulation
starts. During regulation, Vcc of IC7110 will be supplied by
the rectified voltage from winding 7-9 via L5132, D6132 and
C2133.
Control circuit
The control circuit exists of IC7110, C2102, C2104, C2107,
C2109, C2110, R3102, R3103, R3104, R3107, R3108,
R3109 and R3110. C2102 and R3110 define the frequency
of the oscillator.
Power switch circuit
This circuit comprises MOSFET 7125, Rsense 3126, 3127
and 3128, R3125, C2127, L5125, R3112 and R3113. R3125
is a pull-down resistor to remove static charges from the gate
of the MOSFET.
3
ch1 : Drain voltage
ch2 : Oscillator voltage
CH1 1
CH3 20mV~ ALT MTB5.00us- 0.90dv ch1-
ch1
ch3
PM3394B
1
T
3
ch1 : Drain voltage
ch3 : Sense voltage
Figure 8-14
CL 06532151_022.eps
301100
Regulation circuit
The regulation circuit comprises opto-coupler 7200 which
isolates the error signal from the control IC on the primary
side and a reference component 7201. The TL431(7201) can
be represented by two components:
•a very stable and accurate reference diode
•a high gain amplifier
K
R
2.5V
A
CL 06532151_023.eps
Figure 8-15
TL431 will conduct from cathode to anode when the
reference is higher than the internal reference voltage of
about 2.5V. If the reference voltage is lower, the cathode
current is almost zero.
The cathode current flows through the LED of the optocoupler. The collector current of the opto-coupler flows
through R3106, producing an error voltage, connected to
voltage feedback pin 14 of IC7110.
271100
Overvoltage protection circuit
This circuit consist of D6114, C2114, R3115and R3116.
Page 62
GB 62CDR7798.
K
K
K
K
K
K
)
Faultfinding Guide
When the regulation circuit is interrupted due to an error in
the control loop, the regulated output voltage will increase
(overvoltage). This overvoltage is sensed on the primary
winding 7-9. When an overvoltage longer than 2.0µs is
detected, the output is disabled until Vcc is removed and then
re-applied. The power supply will come in a hiccup mode as
long as the error in the control loop is present.
8.2.8Troubleshooting PSU CDR3-ECO
Faultfinding diagram
TROUBLE SHOOTING POWER SUPPLY
Check DC voltages
+5V +12V -8V VFTD(-38V) VDC1-VDC2(3V8)
Disconnect the power supply from the MAIN Board
Connect a dummy load resistor 6,8 ohm 10W (min 5W)
on the 5V and
NO
Secondary rectifier/smoothing circuit
There are 5 rectifier/smoothing circuits on the secondary
side. Each voltage depends on the number of windings of the
transformer.
The -8V supply is regulated by voltage regulator 7249.
On/off circuit
In off mode pin 1 and pin 2 of connector 0206 are connected.
The high voltage (-8V, +12V) over opto coupler 7200 forces
this one to conduct . IC 7110 is switched off
OK
power supply OK
+5V +12V -8V VFTD(-38V) VDC1-VDC2(3V8)
Check DC voltages
NO
Check the +5V
NO
OK
OK
connect the mains inlet to a mains
isolated variac
turn input voltage up and check across
C2121 the voltage
this voltage should be +/- 1,41 x Vin ac
OK
is power supply ticking?
NO
check Vcc on pin 7 IC7110
Vcc = 12V...... 16V
OK
check oscillator on pin 4 IC7110
is the osc +- 30kHz working ?
OK
check the voltage on the source of 7125
Vsource = 1,3V ?
NO (Vsource = +- 0.8V
power supply OK
OK
check - main board
check the fault voltage path
check 6210-2210-2253-5210
NO
check the functionality of the following components:
1120-2121-2125-2126-2127-6102-7125
YES
check the load on the secundairy output
check overload circuit 6141-7141-7150
Disconnect diode 6150
start variac from 0V and turn-up slowly
measure the 5V output
If the 5V becoming higher than 5V, the regulator
circuit are damaged
5V OK
After the power repaired check the 3,3V
5V NOK
check:3201-3202-3203-3204-3205
3206-3207-3208-7131-7201
replace 7110
check circuit around Ic7110
CL 06532151_024.eps
271100
Figure 8-16
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GB 63CDR7798.
8.3CD Main Board
The CD main board is built around the compact disc
mechanism VAM1250 and a loader 1250. The CDM delivers
diode signals and an unequalised high frequency signal.
These signals are necessary inputs for the decoder CD10.
Based on these signals the decoder will control the disc. The
decoder is able to control the sledge, focus motor, radial
motor and turn table. When everything is "locked", the
decoder delivers a digital output according to IEC958
standard, subcode to the microprocessor and I2S for
reproducing analog audio signals by means of a D/A
converter.
The microprocessor controls the CD10 and is slave of the
master processor on the CDR main board in the CDR779.
Both processors communicate via a DSA connection (data,
strobe and acknowledge).
CDM VAM1250
Trigenta
HF ampl.
Diode signals
Radial, focus
Motor, sledge
CD10
SERVO
DECODER
Loader assy
PROCESSOR
UDA1320
DAC
DSA
IIS, DOBM
ANA OUT
CL96532086_048.eps
080999
8.3.2Clock Signals
Description
The microprocessor has its own Xtal or resonator of 12MHz.
The CD10 needs a clock of 8.4672MHz + 100ppm. This
speed also relates to the disc speed. To avoid locking
problems between the two drives in the CDR779, both drives
run on the same clock. Therefore the CD main board gets the
clock for the decoder from the CDR main board via pin 2 of
connector 1208.
The DAC needs a system clock to drive its internal digital
filters and to clock the I2S signals from the decoder. In our
case this is 11.2896MHz (CL11) generated by the CD10.
Measurements
•Connect the power supply as described above in "1.1.1.
Supply Voltages".
•Connect on pin 2 of position 1208 a clock signal of
8.4672 MHz ( 100ppm minimum rise time of 50ns and at
TTL level (0V and +5V).
•Keep microprocessor 7202 in reset by forcing pin 7 at
position 1208 to +5V.
•Release the reset. Now, the processor will reset the
CD10 for at least 75µs.
•The output clock CL11 should be available now at pin 42
of the CD10.
Check the following frequencies :
Figure 8-17
8.3.1Supply Voltages
Description
The CD main board receives +5V and +12V from the CDR
main board via respectively pin 16 and pin 15 of connector
1208. The +5V is split up into +5VHF and +5V. The +5VHF
is used mainly for the diode currents and the HF-amplifier.
The +5V is used for the digital part of the board. On the board
a +3V3 is made from the +5V for the decoder CD10 and an
A3V3 for the DAC UDA1320. The +12V is split up into A12V
for the audio output stage and +12V for the power drivers of
the CDM.
Measurements
Connect following supplies to next pins :
•+5V + 5% to pin 16 of connector 1208.
•+12V + 5% to pin 15 of connector 1208.
•Ground reference to pin 17 of connector 1208.
Keep microprocessor 7202 in reset by forcing pin 7 of
connector 1208 to +5V. Check the following voltages :
PointVoltage
Position 1000 pins 1,3
Position 7000 pins 5,17,21,57
Position 7005 pin 14
Position 7020 pins 25
Position 7020 pins 26,27,28
Position 7021 pin 5
Position 7022 pin 5
Position 7025 pin 16
Position 7202 pin 38
Position 7309 pins 4,13
Position 7120 pin 8
Position 7000 pin 16
Position 7202 pins 14,15
Position 7309 pin 6
Position 7309 pin 1
Position 7309 pin2
8.4672 MHz ± 100ppm
12MHz ± 5%
11.2896 MHz ± 100ppm
2.1168 MHz ± 100ppm
44.1kHz ± 100ppm
Figure 8-19
8.3.3CD10 Decoder/Servo SAA7324 (7000)
Description
The CD10 is a single chip combining the functions of a CD
decoder, digital servo and bitstream DAC. The decoder/
servo part is based on the CD7. The decoding part supports
a full audio specification and can operate at single speed
(n=1) and double speed (n=2).
CL96532086_050.eps
080999
Figure 8-18
Page 64
GB 64CDR7798.
Faultfinding Guide
Block Diagram
12
R1
13
R2
7
V
RIN
40
SCL
39
SDA
41
RAB
42
SILD
2
HFIN
1
HFREF
3
ISLICE
6
I
ref
25
TEST1
31
TEST2
44
TEST3
24
SELPLL
16
CRIN
15
CROUT
26
CL16
49
CL11/4
48
SBSY
47
SFSY
46
SUB
45
RCK
43
STATUS
38
RESET
Pin Configuration
1
HFREF
2
HFIN
3
ISLICE
4
V
SSA1
V
5
DDA1
I
6
ref
V
7
RIN
D1
8
D2
9
D3
10
D4
11
R1
12
R2
13
V
14
SSA2
CROUT
15
CRIN
16
V
V
D1 D2 D3 D4
8910
ADC
V
ref
GENERATOR
MICROCONTROLLER
INTERFACE
FRONT
END
TEST
TIMING
DECODER
MICRO-
CONTROLLER
INTERFACE
SSA2
V
SSA1
4 14 5 17 33 50 585257
11
DIGITAL
PLL
EFM
DEMODULATOR
SRAM
RAM
ADDRESSER
SUBCODE
PROCESSOR
VERSATILE PINS
INTERFACE
63 34 61 6232
V1
V2/V3V4 V5KILL
V
DDA1
DDA2
V
SSD1VSSD3
PRE-
PROCESSING
V
SSD2
CONTROL
PART
PROCESSOR
PEAK
DETECT
CONTROL
FUNCTION
AUDIO
KILL
V
DDD1(P)VDDD2(C)
OUTPUT
MOTOR
CONTROL
ERROR
CORRECTOR
FLAGS
INTERFACE
INTERFACE
(LOOPBACK)
INTERFACE
BITSTREAM
Figure 8-20
SSD3
DDD2(C)
FO
SL
V
LDON
64
V5
V1
62
63
MOTO1
V4
MOTO2
60
61
V
55
56
57
58
59
SAA7324
171819202122232425262728293031
pos
LP
neg
VDDA2
LN
V
RP
RN
V
SELPLL
TEST1
CL16
DDD1(P)
RA
54
DATA
CFLG
53
WCLK
V
52
SCLK
DOBM
514950
EF
Figure 8-21
54
55
STAGES
56
64
59
60
53
51
EBU
30
29
SERIAL
DATA
28
27
37
SERIAL
35
DATA
36
20
21
18
DAC
19
22
23
CL96532086_051.eps
080999
SSD2
CL11/4
V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
KILL
TEST2
CL96532086_052.eps
080999
RA
FO
SL
LDON
MOTO1
MOTO2
CFLG
DOBM
EF
SCLK
WCLK
DATA
SCLI
WCLI
SDI
V
neg
V
pos
LN
LP
RN
RP
SBSY
SFSY
SUB
RCK
TEST3
STATUS
SILD
RAB
SCL
SDA
RESET
SCLI
SDI
WCLI
V2/V3
V
SSD1
8.3.4TDA7073A Power Drivers (7021, 7022)
Description
The TDA7073A is a dual power driver circuit for servo
systems with a single supply. In this configuration it is used
to drive the sledge, tray, focus and radial.
Measurements
Keep microprocessor 7202 in reset by forcing pin 7 of
connector 1208 to +5V. Connect the power supply as
described above in "1.1.1. Supply Voltages". Check the
following voltages :
This component is a 3 phase, full wave pseudo linear driving
system with inbuilt Hall Bias circuit and 3 phase parallel
output.
Measurements
Keep processor 7202 in reset by forcing pin 7 of connector
1208 to +5V. The outputs 9, 10, 11 of connector 1006 are 0V.
Pin 21 of the motor driver 7020 is 2.5V ( 10%.
Pin 22 of the motor driver 7020 is 2.5V ( 10%.
Pin 23 of the motor driver 7020 is 0V.
Pin 19 of the motor driver 7020 is 5V ( 10%.
Put the processor out of reset to continue the measurement.
Check MOT1 at pin 59 of CD10. The duty cycle of the output
should be 50%. Check wave form at pin 11 of 7005-D :
amplitude 5V + 5% duty cycle 50%.
The motor driver 7020 can be measured dynamically by
connecting a hall motor to the application panel. Apply a
pulse of 1V 10Hz and 15% duty cycle to pin 22 (Ec) as input
value with reference to pin 21 (Ecr=2.5V). Measure the
output signals on the driver. This will give as response a
square wave on pin 17 and pin 18. When a positive voltage
080999
080999
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Faultfinding Guide
GB 65CDR7798.
is applied, the square wave on pin 17 will go ahead of the
square wave on pin 18.
All signals will have a value as shown in the truth table.
Check the following output signals :
Motor controller truth table
Input conditions conn 1006 pinOutputs conn 1006Test points on driver
The tray control consists of a TDA7073A power driver (7021)
controlled by the processor 7202 via pin 19 TRAYIN and pin
20 TRAYOUT. If pin 20 is low and pin 19 high, the TRAY+
signal at pin 16 of 7021 is forced to +8V and the TRAY- signal
at pin 13 of 7021 to GND : the tray will open. If pin 20 is high
and pin 19 low, TRAY+ becomes GND and TRAY- becomes
+8V : the tray will close. If pin 19 and 20 of the processor
have the same value, TRAY+ and TRAY- will have the same
value as well : the tray stops moving.
Measurements
Keep procesor 7202 in reset by forcing pin 7 of connector
1208 to +5V. Connect a load of 15Ω, 7W between pin 3 and
4 of connector 1002. Check the voltage over the load with
TRAY+ (pin 3) as positive reference. Check also the levels of
pins 19 and 20 of the processor.
U TRAY+,TRAY- = <100mV
Pin 20 = +5V
Pin 19 = +5V
Force pin 20 of the processor to ground, and check the
voltages.
U TRAY+,TRAY- = -6.5V( 10%
Pin 20 = +0V
Pin 19 = +5V
Force pin 19 of the processor to ground as well and check the
levels again.
U TRAY+,TRAY- = <100mV
Pin 20 = +0V
Pin 19 = +0V
Release pin 20 of the processor and check the levels.
U TRAY+,TRAY- = 6.5V( 10%
Pin 20 = +5V
Pin 19 = +0V
Release pin 19 of the processor and check the levels again:
U TRAY+,TRAY- = <100mV
Pin 20 = +5V
Pin 19 = +5V
Figure 8-25
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GB 66CDR7798.
Faultfinding Guide
8.3.7HF Path
Description
The pre-amplified HF-signal is presented to both n=1 and
n=2 amplifier circuits. The mux/demux switches via software
and micro processor controlled S1 and S2 lines between
either one of the amplified n=1 or n=2 signals. The signal will
n-dependant filtering
+5VHF
PRE AMP
HF
3173
430R
F157
n=2 AMP
3191
430R
n=1 AMP
3174
430R
2143
330p
2
3192
430R
2164
180p
2140
HFGND
2162
HFGND
180p
100p
+5VHF
3188
3203
2K7
7009
BFS20
2K7
HFGND
3169
7023
BFS20
3180
HFGND
2K7
2K7
HFGND
DUAL 4 CHANNEL
MUX/DEMUX
+5VHF
HFGND
2141
2n2
2146
1n5
16
7
8
1
5
2
4
12
14
15
11
74HCT4052D
VCC
VEE
GND
0
1
2
3
+5VHF
HFGND
390p
2149
680p
2130
100n
HF
47u
22n
2160
HFGND
HFGND
HF
BC848B
7010
HFGND
1K
3196
BC858B
7007
4x
3189
2161
3193
3205
HFGND
then follow another amplification and filtering circuit. The
filtering again is controlled by the S1 and S2 lines, dependant
on whether the disc starts up (speed n=1, S1 and S2 Low),
disc plays at speed n=1 (S1 Low, S2 High) or disc plays at
speed n=2 (S1 and S2 High).
7025
0
3
G4
0
1
390R
10
9
6
HFGND
3
13
F313
22n
HFGND
HF
F156
9
22n
2137
HFGND
HFIN
3178
2138
1K
S1
S2
HFGND
HFGND
2142
22n
2150
47n
F310
3
7000
SAA7324
F309
1
HFREF
2145
2
3181
22K
F159
3
4
5
HFIN
ISLICE
VSSA1
VDDA1
47p
HF
180R
10K
CL96532086_057.eps
FRONT
END
080999
DC Settings
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Check the following voltages :
ForcePinLocationMeasure
Emitter70062.4 ± 10%
S1 and S2 “HIGH”Collector70101.9 ± 10%
S1 and S2 “LOW”Collector70101.9 ± 10%
S1 and S2 “HIGH”1370251.6 ± 10%
S1 and S2 “LOW”1370251.6 ± 10%
S1 and S2 “HIGH”370253.2 ± 10%
S1 and S2 “LOW”370253.2 ± 10%
CL96532086_058.eps
Figure 8-27
Figure 8-26
080999
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Faultfinding Guide
GB 67CDR7798.
Transfer Characteristics
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
function generator as a sine wave generator with output level
of 1Vtt. Check this AC value with an AC mV-meter connected
to the input (pin 2) of the CD10 (7000) :
AC
Pin 2 at 7000
CL96532086_059.eps
080999
function generator as a sine wave generator with output level
of 500 kHz, 1Vtt. Check this AC value with an AC mV-meter :
CL96532086_060.eps
080999
8.3.8Audio Part - DAC
Description
The DAC used, is the UDA1320 bit stream, continuous
calibration. I2S signals from various formats can be entered
at pins 1,2 and 3. If these signals are in phase with the
delivered system clock at pin 6, the DAC will reproduce
analog output signals at pins 14 and 16. 0dB level is
0.85Vrms. These analog signals are at 1.65Vdc level.
The DAC has features which can be checked on the input
pins. Mute will switch off the analog signals. De-emphasis is
not used, since this is done in the decoder. Attenuation of 12dB is not used because this is also done in the decoder.
I2S
I2S is a kind of digital audio format, consisting out of 3 lines :
CLOCK, WORDSELECT and DATA.
WORD-SELECT
Word select (WS) indicates whether the data-sample is from
the left or the right audio-channel. It has the same frequency
as the sample rate of the digital audio signal. This can be 32,
44.1 or 48kHz. Normal polarity is low for a left sample and
high for a right sample. So within the low state of the WS-line
the data bits for the left channel are transferred, and within
the high state the data bits of the right channel are
transferred.
Figure 8-29
WS
CLK
DATA
Transition of the WS always happens on a falling edge of the
CLK.
DATA
transmitting device, and read by the receiving device. The
position of the DATA-bits within the WS-signal is very
important. There are several formats for this. In our case we
always use Philips I2S format, no Japanese or Sony format.
The number of data-bits per channel depends on the used
devices.
Timing of the I2S-bus, in case of Philips I2S is shown in the
next figure :
LEFT SAMPLERIGHT SAM PLE
MSBMSB
CL96532086_061.eps
080999
Figure 8-30
CLOCK
The CLOCK signal (CLK) indicates when DataTips must be
set, and when DataTips must be read. The frequency
depends on the speed of the I2S-bus, but is always a factor
of the frequency of the WS-signal. It can be 48x, 64x, 96,
128x... .In our case it is 48x the sample rate frequency =
2.1168MHz. The signal is in phase with the WS-signal.
Page 68
GB 68CDR7798.
Measurements
Faultfinding Guide
IIS
22
DACAMPLIFIER
CLK11
25
NMUTE
Keep processor 7202 in reset by forcing pin 7 of connector
1208 to +5V. This puts the processor outputs in tristate.
Check the reset at pin 4 of processor 7202 to make sure that
the processor is in reset.
Now, force port 0-4 pin 33 at 7202 to 0V to set the decoder
outputs (SCLK, WCLK, DATA, and CL11).
Check the MUTE pin 11 at 7309 : this pin should be low.
Connect via an I2S generator I2S-signals to the DAC :
Pin 1 at 7309: SLCK.
Pin 2 at 7309: WCLK.
Pin 3 at 7309: DATA.
Connect also the SYSCLK pin 6 at position 7309 to a clock
signal of 11.2896 MHz ( 100ppm.
Generate an I2S signal equivalent with a sine wave of 1kHz
at 0dB for both left and right channels.
Check if 0.8 VRMS at pins 14 and 16 at location 7209 with a
DC of 1.65VDC.
Check if 1.7 VRMS ( 2 dB at connector pins 1and 3 at location
1209.
Force MUTE Pin 11 at 7309 high.
Measure again at pins 1 and 3 at location 1209 : both signals
should be at -90 dB.
Figure 8-31
1200 - 17
1200 - 19
CL96532086_062.eps
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Page 69
9.List of Abbreviations
SIGNAL NAMESIGNAL FLOWFUNCTION AND DESCRIPTION
+12Vmain supply voltage from PSU+12V supply voltage from PSU
+12VAsupply voltage+12V supply voltage for Audio part
+5Vmain supply voltage from PSU+5V supply voltage from PSU
+5VAsupply voltage+5V supply voltage for Audio part
+9SRVPWRIC7558 ->- IC7240PoWeR supply for SeRVo driver IC
12VPWRsupply voltage+12V supply voltage for servo part
-8Vmain supply voltage from PSU-8V supply voltage from PSU
-8VAsupply voltage-8V supply voltage for Audio part
A(1:20)IC7701 -> R3818,R3819, R3820, R3821,
R3897 -> IC7703
A(10:20)IC7701 -> R3819, R3820, R3821 ->
IC7702
A1IC7010 -> IC7270amplitude of the “land” reflection relative to the average EFM, voltage
A1LF, A2LFCONN1000 -> IC7010satellite photo diodes A1, A2 current output
A2IC7010 -> IC7270amplitude of the “pit” reflection relative to the average EFM, voltage
A-8Vsupply voltage-8V supply voltage for servo part
AEGERAnalog Error signal GEnerator for Recordable
AINTONIC7008 -> IC7010Alpha INTegrator ON (to AEGER)
ALEIC7270 -> R3213 -> IC7209,
IC7300IC7270 -> R3230
ALPHA0IC7270 -> IC7010analog voltage mode output from OPC D/A converter
ALSIC7008 -> IC7010Alpha Loop Switch (to AEGER)
ASTROBEIC7008 -> IC7010Alpha STROBE (to AEGER)
ATIPAbsolute Time In Pre-groove (sync signal)
ATIPSYNCIC7300 -> IC7270ATIP SYNC signal
ATTIC7270 -> R3717, R3722IC7270 ->
IC7701
B1LF, B2LFCONN1000 -> IC7010satellite photo diodes B1, B2 current output
BCLKIC7701 -> R3898A -> IC7300I2S1 BitCLocK from DASP to CDR60 (playback and record)
BE_RESETIC7701 -> R3261 -> IC7270IC7701 ->
R3716
BIASCIC7008 -> R3056BIAS Current switch CDRW output