Philips CD basic Service Manual

0 (0)

Portable CD 1996

KEY COMPONENTS

BATTERY CHARGING

DC/DC-CONVERTER

TABLE OF CONTENTS
INTRODUCTION ..........................................................................................................	2
KEY COMPONENTS
CDM12.3BLC Compact disc drive.............................................................................	3
SAA7372GP CD-decoder&digital servo IC................................................................	4
SM5856A1F Anti-shock memory controller .............................................................	13
BATTERY CHARGING
Basic considerations................................................................................................	15
PWM-ADC ...............................................................................................................	15
Generation of PWM-signal ......................................................................................	15
Measurement of comparator high time....................................................................	15
Adjustment of PWM-value .......................................................................................	16
Switch off criterion detection....................................................................................	16
Charge timing ..........................................................................................................	16
Trickle charge ..........................................................................................................	16
DC/DC-CONVERTER
Basic considerations................................................................................................	17
Working principle of a standard DC/DC-upconverter ..............................................	17
Generation of control signal.....................................................................................	17
Improvements of standard DC/DC-upconverter ......................................................	18
ABBREVIATIONS......................................................................................................	19

Published by Philips Consumer Electronics Printed in The Netherlands Copyright reserved Subject to modification

CS 46 360

INTRODUCTION

The booklet on hand describes the most important innovations and changes in the world of portable CD for the year of 1996. It should be seen as an addendum to the “System Description Portable CD ´94” – 4822 725 24941.

Because some chapters of this addendum refer to basics, already described in the above mentioned booklet, the user should take care to have both manuals available.

Contents of the System Description Portable CD ´94

•Principles of shock absorbing CD-players

•Compact disc mechanism CDM12.3B/CDM12.3BL

•Key components

HF-amplifier TDA1302

Digital servo controller TDA1301T Signal processor SAA7345

Shock absorbing RAM addresser SAA7346 D/A-converter TDA1345, TDA1305T

• Wired remote control system

The booklets are written for service trainee and everybody who wants to get rid of the basics behind. They cover both, fundamentals and new technologies in portable CD-players.

The ´94 edition mainly refers to circuit diagrams of the so-called “HILLARY-range”, a product family that consists of the typenumbers AZ683x, AZ684x and AZ685x.

The ´96 edition refers to circuit diagrams of the “SHARON-range”, typenumbers AZ726x, AZ736x and AZ746x.

CS 46 361

CDM12.3BLC – COMPACT DISC DRIVE

Mechanical dimensions

The CDM12.3BLC is the successor of the CDM12.3BL, further optimized for low power consumption.

Just as the CDM12.3BL a two stage three spot system with single foucault focus error detection and an integrated optical pick-up is used.

For description of lightpath, focus error detection and radial tracking see chapter “CDM12.3B” of booklet “Portable CD ´94”.

Technical specification CDM12.3BLC

Focus/radial tracking actuator	CDM12.3BLC
Working area:
focus	±0.5mm
radial tracking	0.35mm min.
DC sensitivity:
focus	1mm/V ±20%
radial tracking	0.24mm/V ±20%
AC sensitivity (200Hz):
focus	0.16N/A ±20%
radial tracking	0.25N/A ±20%
Resonance frequency:
focus	30Hz +7Hz
radial tracking	49Hz ±5Hz
Coil resistance:
focus	7.1Ω ±15%
radial tracking	18Ω ±15%
Laser diode
Laser wavelength (30°C)	780nm ±20nm
Max. power intensity out of lens	≤ 0.5mW
Nom. laser current	36mA (47mA max.)
Slide motor
Motor type	FF-030PK-08250
Resistance (20°C)	13.8Ω ±10%
Starting voltage in application	0.6V typ. (1.2V max.)
Disc readout diameter	47.4...117.5mm
Turntable motor
Motor type	RF-410CH-12250
Resistance (20°C)	5.7Ω ±8%
Operating voltage in application	0.5V typ.

Handling recommendations

•Storage in dusty environments should be avoided.

•To avoid damage of the LDGU by electrostatic discharges, measuring equipment and operators should be grounded during handling.

•Contamination of the objective lens will influence the performance. Avoid fingerprints on the lens, handle the CDM in a clean environment.

•The actuator with lightpath has been adjusted carefully during manufacturing. Avoid high forces on this part. Do not disassemble or re-adjust.

•The laserbeam may damage the human eye. Do not look directly into the objective lens.

•Fast heating up (e.g. by bringing the CDM from a cold place into a warm and humid room) can result in moisture condensating on the lens thus influencing the playability for a certain time. Before checking the performance the CDM should stabilize for at least 30 minutes.

14.4	13.2		10.1	14.1
			1
			Ø 8.5
			Ø 11
		61	6
		40°	for servos&disc motor
		40°	flex-foil
			flex-foil
34.5	25	8.5	26.5
45	31.5		39.5
			flex-foil for lightpen
		°
		50
			5
			12
			24.5
		82.5	16.2

Flex-foils for lightpen, servos & disc motor

	1	LASER		1	INNERSW

	2	MONITOR		2	GND

	3	VREF		3	DM+

	4	VREVERSE		4	DM-

	5	R2		5	SLM+

	6	D1		6	SLM-

	7	D2		7	RAD-

	8	R1		8	FOCUS+

	9	D3		9	FOCUS-

	10	GND		10	RAD+

Foil for lightpen			Foil for servos & disc motor

CS 46 362

SAA7372GP – CD-DECODER &

DIGITAL SERVO IC “CD7”

GENERAL DESCRIPTION

The CD7 is a single chip combining the functions of a CD-decoder and a digital servo controller. The decoder part of the CD7 is based on the SAA7345GP (CD6), with an improved error correction strategy. The digital servo part of the CD7 is based on the TDA1301 (DSIC2), with improved performance.

FUNCTIONAL DESCRIPTION DECODER PART

The decoder part of the CD7 has the following features:

•Single and double speed mode

•Lock to disc mode

•On-chip clock multiplier allows use of 8.4672MHz crystal

•Data slicer and clock generator

•Demodulator

•Subcode data processing

•FIFO and full error corrector (t=2, e=4)

•Audio processing block (incl. oversampling)

•DAC, EBU and CD-graphics interface

•Versatile pins interface

•Spindle motor control

Data flow within the decoder part

FRONT-END

HF-IN	DATA
	SLICER
	DPLL		P		SDA
	DPLL		INTERFACE		SDA
			INTERFACE
	DEMODULATION BLOCK
			CD-GRAPH.		SBSY
	EFM	FIFO	CD-GRAPH.		SFSY
	EFM	FIFO	INTERFACE		SFSY
			INTERFACE		SUB
					SUB
	ERROR	SUBCODE	EBU		DOBM
	CORRECT.	PROCESS.	INTERFACE		DOBM
	CORRECT.	PROCESS.	INTERFACE
		SUBCODE PROCESSING BLOCK
	FADE/MUTE	DIGITAL	DE-	AUDIO	SCLK
	FADE/MUTE	DIGITAL	DE-	AUDIO	WCLK
	INTERPOL.	FILTER	EMPHASIS	INTERFACE	WCLK
	INTERPOL.	FILTER	EMPHASIS	INTERFACE	DATA
					DATA
		KILL			KILL
		CIRCUIT			KILL
		CIRCUIT
			AUDIO PROCESSING BLOCK

Demodulator

The demodulator decodes the 14bit EFM data and subcode words into 8bit symbols. It also incorporates an RL2 error correction circuit. Every symbol detected as RL2 will be will be pushed back to RL3. To do this the phase error of both EFM edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability.

Subcode data processing

The 96bit Q-channel word is stored in an internal buffer. The last 16bits are used to internally to perform a CRC. If the data is good, SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the status signal if selected by status control register (see section “CD7 decoder register list”). Q-channel data can also be read via the µP-interface.

Subcode interface V4

Data from the subcode channels Q...W can be read via the V4-pin if selected by the versatile pins register (see section “CD7 decoder register list”). The format is similar to RS232, as shown below.

≥200/n s

11.3/n s

≥11.3/n s

≤ 90/n s

W96

The subcode sync word is formed by a minimum pause of 200/n µs. Each subcode byte starts with a “1” followed by 7bits (Q...W). The gap between bytes is variable between 11.3/n µs and 90/n µs.

Subcode data is also available in the EBU output of the CD7 (DOBM-pin) in a similar format.

CD-graphics interface

Data from the subcode channels P...W can be read via the CD-graphics interface which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3-wire or 4-wire interface by the CD-graphics interface register

(see section “CD7 decoder register list”).

The output format of the interface is shown below.

SBSY

SFSY

RCK

SUB

W96

Crystal oscillator and decoder speed

The oscillator of the CD7 is a conventional two pin design, running at 8...35MHz. It is capable of operating with both, crystals and ceramic resonators, as well as fundamental and third overtone crystals.

Normal oscillation frequencies required are 8.4672MHz, 16.9344MHz, or 33.8688MHz depending on the internal clock settings and usage of the internal clock multiplier PLL. Two decoder speeds are possible on the SAA7372.

Data slicer and clock regenerator

The CD7 has an integrated slice level comparator which is clocked by one of the three crystal oscillator frequencies. The slice level is controlled by an internal current source applied to an external capacitor.

Regeneration of the bit clock is done with an internal fully digital PLL. No external components are required. The DPLL has two control registers for bandwidth and equalization (see section “CD7 decoder register list”).

CS 46 363

Remark: The RCK clock signal is supplied by another device such as a CD-graphics decoder.

FIFO and error corrector

The CD7 has an internal ±8 frame FIFO buffer, used to cover speed deviations of the turntable motor. If an overflow occurs during playback (e.g. as result of a rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator will be activated in order to minimize the effect of data loss (see section “Error concealment”).

The error corrector is a t=2, e=4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) data frames. Four symbols are used from each frame as parity symbols. This error correction algorithm can correct up to two errors on C1 level and up to four errors on C2 level (that is the maximum level of error correction available).

The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector can not ascertain if the symbols are definitely good. C1 generates output flags which are read (after de-interleaving) by C2, to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM-pin) and the EF-output with I2S for CD-ROM applications.

Flags output CFLG

The flags output pin CFLG (open drain) shows the status of the error corrector and interpolator. It is updated every frame (7.35 n kHz). The output format is shown below.

CFLG

33.9/n s

11.3/n s

33.9/n s

The different flags have the following meanings:

F1	F2	F3	F4	F5	F6	F7	F8	FUNCTION
0	X	X	X	X	X	X	X	No absolute time sync
1	X	X	X	X	X	X	X	Absolute time sync
X	0	0	X	X	X	X	X	C1 frame contained no errors
X	0	1	X	X	X	X	X	C1 frame contained 1 error
X	1	0	X	X	X	X	X	C1 frame contained 2 errors

X	1	1	X	X	X	X	X	C1 frame uncorrectable
X	X	X	0	0	X	X	0	C2 frame contained no errors
X	X	X	0	0	X	X	1	C2 frame contained 1 error

X	X	X	0	1	X	X	0	C2 frame contained 2 errors

X	X	X	0	1	X	X	1	C2 frame contained 3 errors
X	X	X	1	0	X	X	0	C2 frame contained 4 errors
X	X	X	1	1	X	X	1	C2 frame uncorrectable

X	X	X	X	X	0	0	X	No interpolations

X	X	X	X	X	0	1	X	At least one 1-sample interpolation
X	X	X	X	X	1	0	X	At least one hold and no interpolations

X	X	X	X	X	1	1	X	At least one hold and one 1-sample int.

EBU interface

The digital output signal at the DOBM-pin of the CD7 is according the IEC958 specification. The format consists of 32bit words (so called “subframes”), transmitted in biphase mark code (two transitions for a logic “1” and one transition for a logic “0”). Subframes are transmitted in blocks of 384. The 32bits of one subframe have the following meaning:

BIT No	NAME	FUNCTION
0...3	sync	sync word B, M or W (see below)
4...7	auxiliary	not used (normally zero)

8...27	audio sample	2´s compliment, MSB=bit 27

28	validity flag	valid=“0”
29	user data	used for subcode data Q...W
30	channel status	control bits and category code

31	parity bit	even parity for bits 4...30

Sync word

The sync word is formed by violation of the biphase rule and does not contain any data. It is used for synchronization. The length is equivalent to 4 data bits. Three different sync patterns indicate the following situations:

SyncB : Start of a new block, audio sample=left channel SyncM : Start of a new subframe, audio=left channel SyncM : Start of a new subframe, audio=right channel

Audio sample

Left and right audio channels are transmitted alternately.

Validity flag

The validity flag indicates uncorrectable audio samples. This flag remains the same even if data is taken after error concealment.

User data

The user data carries the subcode bits Q...W. User data is transmitted asynchronous with the block rate.

Channel status

The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The bit assignment is shown in the table below:

BIT No	NAME	FUNCTION
0...3	control	copy of checked Q-channel bits 0...3
		bit2=“1”: copy permitted
		bit3=“1”: recording has pre-emphasis
4...7	reserved	always zero
8...15	category code	CD: bit8=“1”, all other bits=“0”

16...27	reserved	always zero
28...29	clock accuracy	set by EBU control register
		“00”=level II, “01”=level III, “10”=level

30...191	reserved	always zero

The CD7 has three different EBU modes, selectable via the EBU output format register (see section “CD7 decoder register list”).

Audio functions

Error concealment

A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. Left and right channels have independent interpolators. The erroneous sample is replaced by a level midway between the preceding and following sample. If more than one consecutive uncorrectable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample.

Interpolation	Hold
	Interpolation

Error

Error Error Error

In CD-ROM modes error concealment is not executed.

De-emphasis and phase linearity

When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase linearity of the digital oversampling filter to ≤ ±1° within the band 0...16kHz. With de-emphasis the filter is not phase linear.

If the de-emphasis signal is set to be available at the V5-pin of the versatile pins interface (see section “CD7 decoder register list”), the de-emphasis filter is bypassed and an external circuit can be used.

CS 46 364

Digital oversampling filter

The CD7 includes a 2 to 4 times oversampling IIR-filter. Oversampling is selected via the DAC mode chosen (see section “DAC interface”).

The filter specification of the 4 times oversampling filter is given in the table below:

PASSBAND	ATTENUATION
0...19kHz	≤ 0.001dB
19...20kHz	≤ 0.03dB
STOPBAND	ATTENUATION
24kHz	≥25dB
24...27kHz	≥38dB

27...35kHz	≥40dB
35...64kHz	≥50dB
64...68kHz	≥31dB

68kHz	≥35dB
69...88kHz	≥40dB

The attenuations do not include the sample and hold at the DAC output or the DAC post filter.

When using the oversampling filter, the output level is scaled -0.5dB down, to avoid overflow on full-scale sinewave inputs (0...20kHz).

Mute, attenuation and fade

The CD7 incorporates a digital level controller which performs the functions of soft mute, attenuation and fade. The features are selectable via the fade and attenuation register (see section “CD7 decoder register list”).

Mute

The mute command ramps the audio signal level to zero in a maximum of 128 steps (depending on the current position of the fade counter). Ramping from full scale to zero level takes 3/n ms.

Attenuate

The attenuate command scales the audio signal level to -12dB of full scale.

Fade

Fade activates a 128 stage counter which allows the audio signal level to be scaled up/down. The fade counter is controlled by the stepup/stepdown commands. If the fade level is controlled in a continuous way, a pause of at least 22/n ms must take place between any two stepup or stepdown commands.

Full scale

The full scale command ramps the audio signal level back to full scale. Ramping from mute to full scale takes 3/n ms.

Peak detector

The peak detector of the CD7 measures the highest audio level (absolute value) on positive peaks for the left and right channel. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81...88 contain the left peak value (bit88=MSB), and bits 89...96 contain the right peak value (bit96=MSB). The values are reset after reading the Q-channel data via the µP-interface.

Kill circuit

The kill circuit detects digital silence by testing for an all-zero or all-ones data words in the left or right channel before the digital filter. The output is switched LOW if silence has been detected for at least 250ms. When mute is active, or CD7 is in CD-ROM mode, the kill output is forced LOW.

DAC interface

The CD7 is compatible with a wide range of D/A converters. The supported formats are shown in the table below:

REG.	fs	BITS	SCLK [MHz]	FORMAT	INTERPOL.
1010	fs	16	2.1168 n	I2S CD-ROM mode	no
1011	fs	16	2.1168 n	EIAJ CD-ROM mode	no
110X	4fs	18	8.4672 n	I2S - 18bit	yes
1111	2fs	16	4.2336 n	I2S - 18bit	yes
1110	fs	16/18	2.1168 n	I2S - 16/18bit	yes
000X	4fs	16	8.4672 n	EIAJ - 16bit	yes
0011	2fs	16	4.2336 n	EIAJ - 16bit	yes
0010	fs	16	2.1168 n	EIAJ - 16bit	yes
010X	4fs	18	8.4672 n	EIAJ - 18bit	yes
0111	2fs	18	4.2336 n	EIAJ - 18bit	yes
0110	fs	18	2.1168 n	EIAJ - 18bit	yes

All formats are MSB first. The sampling frequency fs depends on the disc speed n and is 44.1kHz in single speed mode and 88.2kHz in double speed mode. The polarity of the word clock WCLK and the audio data can be inverted via the DAC output register (see section “CD7 decoder register list”).

I2S-data format (16bit word length shown)

SCLK

WCLK									left channel																	right channel


DATA		15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0		15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0


MISC		MSB C2-error flag													LSB C2-error flag				MSB C2-error flag													LSB C2-error flag
MISC	(only in CD-ROM mode)												(only in CD-ROM mode)					(only in CD-ROM mode)												(only in CD-ROM mode)

EIAJ-data format (18bit word length shown)

SCLK

WCLK			left channel																		right channel


DATA	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0


MISC	MSB C2-error flag								LSB C2-error flag										MSB C2-error flag								LSB C2-error flag
MISC	(only in CD-ROM mode)						(only in CD-ROM mode)												(only in CD-ROM mode)						(only in CD-ROM mode)

Turntable motor control

The turntable motor is controlled by an integrated digital servo. Address information from the internal ±8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by the motor output configuration register (see section “CD7 decoder register list”), are supported:

•PDM-output – 2-line, 1 n MHz sampling frequency

•PWM-output – 2-line, 22.05 n kHz modulation frequency

•PWM-output – 4-line, 22.05 n kHz modulation frequency

•CDV mode

CS 46 365

+ 13 hidden pages