Philips CBTU0808 Technical data

CBTU0808EE/G

CBTU0808

Dual lane PCI Express port multiplexer

Rev. 01 — 2 June 2006

Product data sheet

1. General description

The CBTU0808 is a dual lane port multiplexer designed to provide convenient and reliable path switching for PCI Express signals. It is organized as two PCI Express lanes, each consisting of a Transmit and Receive channel. Each channel has four ports, two (A and B) on the source (or host) side and two (A and B) on the destination (or device) side. Each port provides a pair of signal lines to support PCIe differential signaling.

Using specially designed high-bandwidth and high off-isolation switch elements, source and destination ports can be connected or isolated in three possible configurations: source A and B to destinations A and B respectively; or source A to destination B (remaining ports isolated), or all ports isolated.

The switch elements are controlled by internal control logic to set switch positions in accordance with these three configurations, selectable by CMOS inputs CTRL0 and CTRL1 for lanes 0 and 1 respectively. Within a lane, the switch configuration is always applied identically to both transmit and receive channels.

The CBTU0808 is packaged in a 48-ball, depopulated 9 × 9 grid, 0.5 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum

5 mm × 5 mm of board space) allows for adequate signal routing and escape using conventional board technology.

2. Features

n2-lane wide PCI Express port multiplexer

nOne transmit and one receive differential channel per lane

nFour ports per channel

nPCI Express signaling compliant

nHigh bandwidth: > 1 GHz

nLow OFF-feedthrough of < −35 dB at 1.25 GHz

nLow channel crosstalk of < −35 dB at 1.25 GHz

nDesigned to match characteristic impedance of PCIe signaling environment

nSingle 1.8 V supply operation

nESD resilience of 2 kV HBM

nAvailable in 48-ball, 5 mm × 5 mm, 0.5 mm ball pitch TFBGA package, Pb-free/Green

3.Applications

nHigh-performance computing applications

nPort switching and docking applications

Philips Semiconductors			CBTU0808
			Dual lane PCI Express port multiplexer
4. Ordering information
Table 1. Ordering information
Type number	Solder process	Package
		Name	Description	Version
CBTU0808EE/G	Pb-free (SnAgCu solder ball	TFBGA48	plastic thin fine-pitch ball grid array package;	SOT918-1
	compound)		48 balls; body 5 × 5 × 0.8 mm

5. Functional diagram

		CBTU0808
	CTRL[1:0]	CONTROL AND CONFIGURATION
	TEST[1:0]
	TXSA0P	TXDA0P
	TXSA0N	TXDA0N
	channel Tx0
	TXSB0P	TXDB0P
	TXSB0N	TXDB0N
		LANE 0
	RXSA0P	RXDA0P
	RXSA0N	RXDA0N
	channel Rx0
	RXSB0P	RXDB0P
	RXSB0N	RXDB0N
	TXSA1P	TXDA1P
	TXSA1N	TXDA1N
	channel Tx1
	TXSB1P	TXDB1P
	TXSB1N	TXDB1N
		LANE 1
	RXSA1P	RXDA1P
	RXSA1N	RXDA1N
	channel Rx1
	RXSB1P	RXDB1P
	RXSB1N	RXDB1N
		002aac139

Fig 1. Functional diagram

CBTU0808_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 2 June 2006

2 of 16

Philips Semiconductors	CBTU0808
	Dual lane PCI Express port multiplexer

6.Pinning information

6.1Pinning

ball A1	CBTU0808EE/G
index area
1	2	3	4	5	6	7	8	9
A
B
C
D
E
F
G
H
J

002aac213

Transparent top view

Fig 2. Pin configuration for TFBGA48

	1	2	3	4	5	6	7	8	9
A	CTRL0	TXSB0P		TXSA0P	GND	TXDA0P		TXDB0P	TEST1
B	RXSA0P	GND	TXSB0N	TXSA0N	VDD	TXDA0N	TXDB0N	GND	RXDA0P
C		RXSA0N						RXDA0N
D	RXSB0P	RXSB0N						RXDB0N	RXDB0P
E	GND	VDD						VDD	GND
F	TXSA1P	TXSA1N						TXDA1N	TXDA1P
G		TXSB1N						TXDB1N
H	TXSB1P	GND	RXSA1N	RXSB1N	VDD	RXDB1N	RXDA1N	GND	TXDB1P
J	TEST0	RXSA1P		RXSB1P	GND	RXDB1P		RXDA1P	CTRL1
									002aac212

48-ball, 9 × 9 grid; top view. An empty cell indicates no ball is populated at that grid point.

Fig 3. Ball mapping

CBTU0808_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 2 June 2006

3 of 16

Philips Semiconductors					CBTU0808
				Dual lane PCI Express port multiplexer
6.2 Pin description
	Table 2. Pin description
	Signal group	Symbol	Pin	Type	Description
	Test and	CTRL0	A1	CMOS	Switch configuration control inputs. See
	control			input	Table 3 “Switch configuration truth table”.
		CTRL1	J9
		TEST0	J1	CMOS	Test input. Used for test purposes only.
				input	Should be left open-circuit during normal
					operation. An internal pull-down resistor
					will default this pin to a LOW state.
		TEST1	A9	output	Test output. Used for test purposes only.
					Should be left open-circuit in normal
					application.
	Signal ports	TXSA0P, TXSA0N,	A4, B4,	signal	Transmit ports A and B differential signal
		TXSB0P, TXSB0N	A2, B3	port	terminals for Lane 0, Source side.
		RXSA0P, RXSA0N,	B1, C2,	signal	Receive ports A and B differential signal
		RXSB0P, RXSB0N	D1, D2	port	terminals for Lane 0, Source side.
		TXSA1P, TXSA1N,	F1, F2,	signal	Transmit ports A and B differential signal
		TXSB1P, TXSB1N	H1, G2	port	terminals for Lane 1, Source side.
		RXSA1P, RXSA1N,	J2, H3,	signal	Receive ports A and B differential signal
		RXSB1P, RXSB1N	J4, H4	port	terminals for Lane 1, Source side.
		TXDA0P, TXDA0N,	A6, B6,	signal	Transmit ports A and B differential signal
		TXDB0P, TXDB0N	A8, B7	port	terminals for Lane 0, Destination side.
		RXDA0P, RXDA0N,	B9, C8,	signal	Receive ports A and B differential signal
		RXDB0P, RXDB0N	D9, D8	port	terminals for Lane 0, Destination side.
		TXDA1P, TXDA1N,	F9, F8,	signal	Transmit ports A and B differential signal
		TXDB1P, TXDB1N	H9, G8	port	terminals for Lane 1, Destination side.
		RXDA1P, RXDA1N,	J8, H7,	signal	Receive ports A and B differential signal
		RXDB1P, RXDB1N	J6, H6	port	terminals for Lane 1, Destination side.
	Power	VDD	B5, E2,	power	power supply pins
			E8, H5
		GND	A5, B2,	power	ground pins
			B8, E1,

E9, H2,

H8, J5

CBTU0808_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 2 June 2006

4 of 16

Philips Semiconductors	CBTU0808
	Dual lane PCI Express port multiplexer

7.Functional description

7.1Functional description

7.1.1General information

The CBTU0808 Dual lane PCI Express port multiplexer is designed to allow port switching of up to two PCI Express lanes (each including a Transmit and Receive channel) according to three switch configuration settings (described in Section 7.1.2.1). The basic switch element of the CBTU0808 is designed integrally with its package and chip interconnect to present an optimum characteristic on-impedance when used in a

PCI Express signaling environment, and to provide high off-port isolation and low crosstalk.

7.1.2Functional information

The following paragraphs describe the control and configuration possibilities available in the CBTU0808.

7.1.2.1Switch configuration

The position of the port switches is controlled by CMOS input signals CTRL[1:0] and can be overridden by CMOS input TEST0 to disconnect (open) all ports between source and destination. For a given lane, the switch positions are always identical between transmit and receive channels. Lane 0 is controlled by CTRL0 and Lane 1 is controlled by CTRL1. The truth table for the switch position as a function of these inputs is shown in Table 3.

Table 3. Switch configuration truth table

Inputs						Function
CTRLn		[1]			TEST0	Source ports	[1]		Destination ports		Comment
									A	B
LOW					LOW	An			Ron	high-Z	SA:DA/SB:DB
											(Dual Through mode)
						Bn			high-Z	Ron
HIGH	[2]				LOW	An			high-Z	R	SA:DB
										on	(Single Cross mode)
						Bn			high-Z	high-Z
LOW					HIGH	An			high-Z	high-Z	All ports open-circuit
											(Disconnect mode)
						Bn			high-Z	high-Z
> LOW					HIGH	Test mode for internal use only					do not use

[1]n is the Lane number (0 or 1).

[2]CTRL1 or CTRL0 = HIGH.

CBTU0808_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 2 June 2006

5 of 16