Datasheet BUT18F, BUT18AF Datasheet (Philips)

DISCRETE SEMICONDUCTORS
DATA SH EET
BUT18F; BUT18AF
Silicon diffused power transistors
Product specification Supersedes data of 1997 Aug 13
1999 Jun 11
Silicon diffused power transistors BUT18F; BUT18AF
DESCRIPTION
High-voltage, high-speed, glass-passivated NPN power transistor in a SOT186 package with electrically isolated mounting base.
APPLICATIONS
Converters
Inverters
Switching regulators
Motor control systems.
QUICK REFERENCE DATA
PINNING
PIN DESCRIPTION
1 base 2 collector 3 emitter
mb mounting base; electrically isolated from all pins
ndbook, halfpage
MBB008
23
1
MBK109
Fig.1 Simplified outline (SOT186) and symbol.
2
1
3
SYMBOL PARAMETER CONDITIONS MAX. UNIT
V
CESM
collector-emitter peak voltage VBE=0
BUT18F 850 V BUT18AF 1000 V
V
CEO
collector-emitter voltage open base
BUT18F 400 V
BUT18AF 450 V V I
Csat
I
C
I
CM
P t
f
CEsat
tot
collector-emitter saturation voltage see Fig.7 1.5 V collector saturation current 4 A collector current (DC) see Fig.4 6 A collector current (peak value) see Fig.4 12 A total power dissipation Th≤ 25 °C; see Fig.2 33 W fall time resistive load; see Figs 10 and 11 0.8 µs
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-h
thermal resistance from junction to external heatsink note 1 6.15 K/W
note 2 3.65 K/W
Notes
1. Mounted without heatsink compound and 30 ±5 N force on centre of package.
2. Mounted with heatsink compound and 30 ±5 N force on centre of package.
1999 Jun 11 2
Silicon diffused power transistors BUT18F; BUT18AF
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CESM
V
CEO
I
Csat
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
collector-emitter peak voltage VBE=0
BUT18F 850 V
BUT18AF 1000 V
collector-emitter voltage open base
BUT18F 400 V
BUT18AF 450 V
collector saturation current 4A collector current (DC) see Fig.4 6A collector current (peak value) see Fig.4 12 A base current (DC) 3A base current (peak value) 6A total power dissipation Th≤ 25 °C; see Fig.2; note 1 20 W
T
25 °C; see Fig.2; note 2 33 W
h
storage temperature 65 +150 °C junction temperature 150 °C
Notes
1. Without heatsink compound.
2. With heatsink compound.
ISOLATION CHARACTERISTICS
SYMBOL PARAMETER TYP. MAX. UNIT
V C
isolM isol
isolation voltage from all terminals to external heatsink (peak value) 1500 V isolation capacitance from collector to external heatsink 12 pF
CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CEOsust
collector-emitter sustaining voltage IC= 100 mA; I
BUT18F 400 −−V
L = 25 mH; see Figs 3 and 6
Boff
=0;
BUT18AF 450 −−V V
CEsat
V
BEsat
I
CES
collector-emitter saturation voltage IC= 4 A; IB= 800 mA; see Fig.7 −−1.5 V base-emitter saturation voltage IC= 4 A; IB= 800 mA; see Fig.8 −−1.3 V collector-emitter cut-off current VCE=V
CESMmax
; VBE=0;
−−1mA
note 1 V
CE=VCESMmax
; VBE=0;
−−2mA
Tj= 125 °C; note 1
I
EBO
emitter-base cut-off current VEB=9V; IC=0 −−10 mA
1999 Jun 11 3
Silicon diffused power transistors BUT18F; BUT18AF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
h
FE
Switching times resistive load (see Figs 10 and 11) t
on
t
s
t
f
Switching times inductive load (see Figs 10 and 13) t
s
t
f
Note
1. Measured with a half-sinewave voltage (curve tracer).
DC current gain VCE=5V; IC= 10 mA;
see Fig.9 V
=5V; IC= 1 A; see Fig.9 10 20 35
CE
turn-on time I
storage time I
fall time I
storage time I fall time I
I
I
I
Con Bon
Con Bon
Con Bon
Con Con
=4A; = I
Boff
=4A; = I
Boff
=4A; = I
Boff
= 4 A; I = 4 A; I
= 800 mA
= 800 mA
= 800 mA
= 800 mA 1.6 2.5 µs
Bon
= 800 mA 150 400 ns
Bon
10 18 35
−−1µs
−−4µs
−−0.8 µs
120
handbook, halfpage
P
tot max
(%)
80
40
0
050
100 150
T
h
Fig.2 Power derating curve.
o
(
MGK674
C)
andbook, halfpage
30 to 60 Hz
Fig.3 Test circuit for collector-emitter
100 to 200
L
300
6 V
sustaining voltage.
+ 50 V
horizontal
oscilloscope
vertical
1
MGE252
1999 Jun 11 4
Silicon diffused power transistors BUT18F; BUT18AF
handbook, full pagewidth
10
10
(A)
2
10
I
C
I
CM max
10
I
C max
1
1
2
I
II
DC
MGB922
BUT18F
3
10
4
10
110
Mounted without heatsink compound and 30±5 N force on centre of package. Tmb<25°C I -Region of permissible DC operation. II -Permissible extension for repetitive pulse operation.
10
BUT18AF
Fig.4 Forward bias SOAR.
1999 Jun 11 5
2
3
10
VCE (V)
4
10
Silicon diffused power transistors BUT18F; BUT18AF
10
handbook, full pagewidth
Z
th jmb (K/W)
δ = 1
1
0.75
0.50
0.33
0.20
0.10
1
10
0.05
0.02
0.01
2
10
0
3
10
4
10
MGB866
3
10
2
10
1
10
110
10
tp (s)
2
Fig.5 Transient thermal impedance.
I
handbook, halfpage
C
(mA)
250 200
100
0
min
V
CEOsust
Fig.6 Oscilloscope display for collector-emitter
sustaining voltage.
MGE239
VCE (V)
V
CEsat
2
(1)
(2)
(3)
handbook, halfpage
(V)
1
0
2
10
1
10
110
IB (A)
Tj=25°C. (1) IC=1A. (2) IC=2A. (3) IC=4A.
Fig.7 Collector-emitter saturation voltage as a
function of base current.
MGB884
1999 Jun 11 6
Silicon diffused power transistors BUT18F; BUT18AF
1.5
handbook, halfpage
V
BEsat
(V)
1
0.5
2
10
Tj=25°C. (1) IC=4A. (2) IC=2A. (3) IC=1A.
1
10
110
Fig.8 Base-emitter saturation voltage as a
function of base current.
(1) (2) (3)
IB (A)
MGB880
2
10
handbook, halfpage
h
FE
10
1
2
10
VCE= 5V; Tj=25°C.
Fig.9 DC current gain; typical values.
MBC097
VCE = 5 V
1V
1
10
11010
IC (A)
2
handbook, halfpage
V
IM
0
t
p
T
VCC= 250V; tp=20µs; VIM= 6to +8 V; tp/T = 0.01. The values of RB and RL are selected in accordance with I
requirements.
I
Bon
V
CC
R
L
R
B
D.U.T.
Fig.10 Test circuit resistive load.
MGE244
Con
and
handbook, halfpage
90%
I
B
10%
90%
I
C
10%
tr≤ 20 ns.
Fig.11 Switching times waveforms with
tr ≤30 ns
t
on
resistive load.
MBB731
I
B on
t
I
B off
I
C on
t
f
t
s
t
1999 Jun 11 7
Silicon diffused power transistors BUT18F; BUT18AF
handbook, halfpage
+I
B
V
BE
VCL= 300 V; VCC= 30 V; VBE= 5 V; LB=1µH; LC= 200 µH.
L
V
CC
L
C
B
D.U.T.
Fig.12 Test circuit inductive load.
V
CL
MGE246
handbook, halfpage
90%
I
B
10%
90%
I
C
10%
Fig.13 Switching time waveforms with
t
r
inductive load.
I
B on
t
I
B off
I
C on
t
f
t
s t
off
t
MGE238
1999 Jun 11 8
Silicon diffused power transistors BUT18F; BUT18AF
PACKAGE OUTLINE
Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 exposed tabs SOT186
E
E
1
P
D
1
D
m
q
A
A
1
L
1
b
L
0.55
0.38
1
2
23
1
b
e
e
1
D
17.0
16.4
D
1
7.9
10.2
7.5
REFERENCES
c
w M
0 5 10 mm
scale
E
E
1
5.7
5.3
2.54
9.6
e
e
1
14.3
5.08
13.5
L
DIMENSIONS (mm are the original dimensions)
A
A
b
UNIT
mm
Note
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
OUTLINE VERSION
SOT186 TO-220
4.4
4.0
1
2.9
2.5
b
1
1.5
0.9
1.3
0.7
IEC JEDEC EIAJ
Q
c
(1)
L
1
4.8
4.0
m
L
2
3.2
0.9
10 0.4
3.0
0.5
EUROPEAN
PROJECTION
1.4
1.2
qQPL
w
4.4
4.0
ISSUE DATE
97-06-11
1999 Jun 11 9
Silicon diffused power transistors BUT18F; BUT18AF
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1999 Jun 11 10
Silicon diffused power transistors BUT18F; BUT18AF
NOTES
1999 Jun 11 11
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1999 66
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 135002/02/pp12 Date of release: 1999 Jun 11 Document order number: 9397 750 06093
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