Philips BUK9880-55 Datasheet

Philips Semiconductors Product specification

TrenchMOS transistor BUK9880-55
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope suitable for surface V
mounting. The device features very I
low on-state resistance and has P
integral zener diodes giving ESD T
protection. It is intended for use in R

DS

D

tot
j

DS(ON)

automotive and general purpose resistance VGS = 5 V
switching applications.

PINNING - SOT223 PIN CONFIGURATION SYMBOL

Drain-source voltage 55 V
Drain current 7.5 A
Total power dissipation 1.8 W
Junction temperature 150 ˚C
Drain-source on-state 80 mΩ

PIN DESCRIPTION

4

d

1 gate
2 drain
3 source
4 drain (tab)

1

23

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

D

I

DM

P
P

T

DS
DGR

tot
tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 10 V
Drain current (DC) Tsp = 25 ˚C - 7.5 A
Drain current (DC) On PCB in Fig.2 - 3.5 A

T

= 25 ˚C

amb

Drain current (DC) On PCB in Fig.2 - 2.2 A

T

= 100 ˚C

amb

Drain current (pulse peak value) Tsp = 25 ˚C - 40 A
Total power dissipation Tsp = 25 ˚C - 8.3 W
Total power dissipation On PCB in Fig.2 - 1.8 W

T

= 25 ˚C

amb

Storage & operating temperature - - 55 150 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

April 1998 1 Rev 1.100

Electrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)

Philips Semiconductors Product specification

TrenchMOS transistor BUK9880-55

Logic level FET

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-sp

R

th j-amb

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V

(BR)GSS

R

DS(ON)

From junction to solder point Mounted on any PCB 12 15 K/W
From junction to ambient Mounted on PCB of Fig.18 - 70 K/W

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Tj = 150˚C 0.6 - - V

Tj = -55˚C - - 2.3 V

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 150˚C - - 100 µA

Gate source leakage current VGS = ±5 V - 0.02 1 µA

Tj = 150˚C - - 5 µA
Gate source breakdown voltage IG = ±1 mA 10 - - V
Drain-source on-state VGS = 5 V; ID = 5 A - 65 80 mΩ
resistance Tj = 150˚C - - 148 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
C

C
C

t
t
t
t

fs

iss
oss
rss

d on
r
d off
f

Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C 4 8 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF

Output capacitance - 110 135 pF
Feedback capacitance - 60 85 pF

Turn-on delay time VDD = 30 V; ID = 7 A; - 10 15 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω; - 30 50 ns
Turn-off delay time - 30 45 ns
Turn-off fall time Tj = 25˚C - 30 40 ns

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = -55 to 175˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V
t

rr

Q

SD

rr

Continuous reverse drain Tsp = 25˚C - - 7.5 A
current
Pulsed reverse drain current Tsp = 25˚C - - 40 A
Diode forward voltage IF = 5 A; VGS = 0 V - 0.85 1.1 V

Reverse recovery time IF = 5 A; -dIF/dt = 100 A/µs; - 38 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.2 - µC

April 1998 2 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9880-55

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 2.5 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Tmb / C

= f(Tsp)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tsp); conditions: VGS ≥ 5 V

D 25 ˚C

100

ID/A

RDS(ON) = VDS/ID

10

1

0.1
1 10 100

DC

VDS/V

Fig.3. Safe operating area. Tsp = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

Zth/ (K/W)

100

10

0.5

0.2

0.1

1

0.05

p

0.02

0.1

0.01

1.0E-06 0.0001 0.01 1 100

t/s

t

P

D

p

t

D =

T

t

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-sp

tp =
1 us

10us
100 us

1 ms

10ms

100ms

p

April 1998 3 Rev 1.100