Philips buk98150 55a DATASHEETS
M3D087
1. Description
2. Features
BUK98150-55A
TrenchMOS™ logic level FET
Rev. 01 — 03 October 2000 Product specification
N-channel enhancement mode field-effect powertransistorina plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK98150-55A in SOT223 (SC-73).
■ TrenchMOS™ technology
■ Q101 compliant
■ 150 °C rated
■ Logic level compatible.
3. Applications
c
c
■ Automotive and general purpose power switching:
◆ 12 V and 24 V loads
◆ Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT223 (SC-73), simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
2 drain (d)
3 source (s)
4 drain (d)
123
Top view
SOT223 (SC-73)
1. TrenchMOS is a trademark of Royal Philips Electronics.
4
MSB002 - 1
g
MBB076
d
s
Philips Semiconductors
BUK98150-55A
TrenchMOS™ logic level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
V
I
P
T
R
DS
D
tot
j
DSon
drain-source voltage (DC) − 55 V
drain current (DC) Tsp=25°C; VGS=5V − 5A
total power dissipation Tsp=25°C − 6W
junction temperature − 150 °C
drain-source on-state resistance VGS=5V; ID= 5 A 128 150 mΩ
= 4.5 V; ID=5A − 161 mΩ
V
GS
= 10 V; ID= 5 A − 137 mΩ
V
GS
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
DR
I
DRM
Avalanche ruggedness
W
DSS
drain-source voltage (DC) − 55 V
drain-gate voltage (DC) RGS=20kΩ−55 V
gate-source voltage (DC) −±10 V
non-repetitive gate-source voltage tp≤ 50 µs −±15 V
drain current (DC) Tsp=25°C; VGS=5V;Figure 2 and 3 − 5A
= 100 °C; VGS=5V;Figure 2 − 3A
T
sp
peak drain current Tsp=25°C; pulsed; tp≤ 10 µs;
− 30 A
Figure 3
total power dissipation Tsp=25°C; Figure 1 − 6W
storage temperature −55 +150 °C
operating junction temperature −55 +150 °C
reverse drain current (DC) Tsp=25°C − 5A
pulsed reverse drain current Tsp=25°C; pulsed; tp≤ 10 µs − 30 A
non-repetitive avalanche energy unclamped inductive load; ID=8A;
≤ 25 V; VGS=5V; RGS=50Ω;
V
DS
starting T
sp
=25°C
− 6.4 mJ
9397 750 07576
Product specification Rev. 01 — 03 October 2000 2 of 13
© Philips Electronics N.V. 2000. All rights reserved.
Philips Semiconductors
BUK98150-55A
TrenchMOS™ logic level FET
120
P
der
(%)
100
80
60
40
20
0
0 25 50 75 100 125 150 175
P
P
der
tot
----------------------
P
tot 25 C°()
100%×=
03aa17
Tsp (oC)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
120
I
der
(%)
100
80
60
40
20
0
0 25 50 75 100 125 150 175
03aa25
Tsp (oC)
VGS≥ 4.5 V
I
I
der
D
------------------ -
I
D25C°()
100%×=
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
100
T
=25°C; IDM is single pulse.
amb
I
D
(A)
10
1
0.1
RDSon = VDS/ ID
t
P
t
p
1 10 100
p
δ =
T
t
T
D.C.
VDS (V)
03na29
tp = 10 us
100 us
1 ms
10 ms
100 ms
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 07576
© Philips Electronics N.V. 2000. All rights reserved.
Product specification Rev. 01 — 03 October 2000 3 of 13
Philips Semiconductors
Single Shot
0.2
0.05
0.02
BUK98150-55A
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Value Unit
R
th(j-a)
R
th(j-sp)
thermal resistance from junction to ambient Figure 4 70 K/W
thermal resistance from junction to solder
20 K/W
point
7.1 Transient thermal impedance
100
Zth(j-sp)
(K/W)
10
0.1
0.01
0.5
0.1
1
P
t
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
110
03na30
t
p
δ =
T
p
t
T
2
10
tp (s)
Fig 4. Transient thermal impedance from junction to solder point as a function of
pulse duration.
9397 750 07576
© Philips Electronics N.V. 2000. All rights reserved.
Product specification Rev. 01 — 03 October 2000 4 of 13
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