Philips BUK9635-55 Datasheet
Philips Semiconductors Product specification
TrenchMOS transistor BUK9635-55
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope suitable for surface V
mounting. Using ’trench’ technology I
thedevice features very low on-state P
resistance and has integral zener T
diodes giving ESD protection up to R
DS
D
tot
j
DS(ON)
2kV. It is intended for use in resistance VGS = 5 V
automotive and general purpose
switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
Drain-source voltage 55 V
Drain current (DC) 34 A
Total power dissipation 85 W
Junction temperature 175 ˚C
Drain-source on-state 35 mΩ
PIN DESCRIPTION
mb
d
1 gate
2 drain
3 source
mb drain
2
13
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
±V
I
D
I
D
I
DM
P
T
DS
DGR
tot
stg
GS
, T
j
Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 10 V
Drain current (DC) Tmb = 25 ˚C - 34 A
Drain current (DC) Tmb = 100 ˚C - 24 A
Drain current (pulse peak value) Tmb = 25 ˚C - 136 A
Total power dissipation Tmb = 25 ˚C - 85 W
Storage & operating temperature - - 55 175 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
R
th j-a
April 1998 1 Rev 1.100
Thermal resistance junction to - - 1.75 K/W
mounting base
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient board
Philips Semiconductors Product specification
TrenchMOS transistor BUK9635-55
Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
R
DS(ON)
(BR)GSS
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3
Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - 10 µA
Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
Drain-source on-state VGS = 5 V; ID = 17 A - 28 35 mΩ
resistance Tj = 175˚C - - 74 mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g
C
C
C
t
t
t
t
L
fs
iss
oss
rss
d on
r
d off
f
d
Forward transconductance VDS = 25 V; ID = 15 A 12 - - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 1400 pF
Output capacitance - 205 245 pF
Feedback capacitance - 110 150 pF
Turn-on delay time VDD = 30 V; ID = 15 A; - 14 21 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 77 110 ns
Turn-off delay time Resistive load - 55 80 ns
Turn-off fall time - 48 65 ns
Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die
L
s
Internal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
t
rr
Q
SD
rr
Continuous reverse drain - - 34 A
current
Pulsed reverse drain current - - 136 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 34 A; VGS = 0 V - 1.0 -
Reverse recovery time IF = 34 A; -dIF/dt = 100 A/µs; - 40 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.16 - µC
April 1998 2 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9635-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
Drain-source non-repetitive ID = 20 A; VDD ≤ 25 V; - - 45 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
= f(Tmb)
D 25 ˚C
Normalised Current Derating
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Tmb); conditions: VGS ≥ 5 V
D 25 ˚C
1000
ID/A
100
10
1
1 10 100
RDS(ON) = VDS/ID
DC
VDS/V
tp =
1 us
10us
100 us
1 ms
10ms
100ms
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
ZTH/ (K/W)
10
1
0.5
0.2
p
0.1
0.05
0.1
0.02
0
0.01
1.0E-06 0.0001 0.01 1 100
t
P
D
t/s
t
p
D =
T
t
T
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-mb
p
April 1998 3 Rev 1.100
Loading...