Philips BUK9575-55 Datasheet

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope using ’trench’V
technology.Thedevicefeatures very I
low on-state resistance and has P
integral zener diodes giving ESD T
protectionupto 2kV. Itis intended for R

DS

D

tot
j

DS(ON)

use in automotive and general resistance VGS = 5 V
purpose switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

Drain-source voltage 55 V
Drain current (DC) 19.7 A
Total power dissipation 61 W
Junction temperature 175 ˚C
Drain-source on-state 75 mΩ

PIN DESCRIPTION

tab

d

1 gate
2 drain
3 source

tab drain

123

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 10 V
Drain current (DC) Tmb = 25 ˚C - 19.7 A
Drain current (DC) Tmb = 100 ˚C - 13.9 A
Drain current (pulse peak value) Tmb = 25 ˚C - 79 A
Total power dissipation Tmb = 25 ˚C - 61 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

April 1998 1 Rev 1.100

Thermal resistance junction to - - 2.46 K/W
mounting base
Thermal resistance junction to in free air 60 - K/W
ambient

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V
R

DS(ON)

(BR)GSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Tj = 175˚C - 10 µA
Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
Drain-source on-state VGS = 5 V; ID = 10 A - 60 75 mΩ
resistance Tj = 175˚C - - 157 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
C

C
C

t
t
t
t

L

fs

iss
oss
rss

d on
r
d off
f

d

Forward transconductance VDS = 25 V; ID = 10 A 5 - - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF

Output capacitance - 110 135 pF
Feedback capacitance - 60 85 pF

Turn-on delay time VDD = 30 V; ID = 10 A; - 10 15 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 4770ns
Turn-off delay time Resistive load - 28 40 ns
Turn-off fall time - 33 45 ns

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die

L

d

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

L

s

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V
t

rr

Q

SD

rr

Continuous reverse drain - - 19.7 A
current
Pulsed reverse drain current - - 79 A
Diode forward voltage IF = 19.7 A; VGS = 0 V - 0.95 1.2 V

Reverse recovery time IF = 19.7 A; -dIF/dt = 100 A/µs; - 32 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.12 - µC

April 1998 2 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 10 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

100

ID/A

RDS(ON) = VDS/ID

10

DC

1

1 10 100

VDS/V

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

Zth/ (K/W)

10

0.5

1

0.2

0.1

0.05

0.1

0.02
0

0.01

1.0E-06 0.0001 0.01 1 100
t/s

p

t

P

D

p

t

D =

T

t

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

tp =
1 us

10us

100 us

1 ms

10ms
100ms

p

April 1998 3 Rev 1.100