Philips buk9219 55a DATASHEETS
M3D300
1. Description
2. Features
BUK9219-55A
TrenchMOS™ logic level FET
Rev. 01 — 24 October 2000 Product specification
N-channel enhancement mode field-effect powertransistorina plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9219-55A in SOT428 (D-PAK).
■ TrenchMOS™ technology
■ Q101 compliant
■ 175 °C rated
■ Logic level compatible.
3. Applications
■ Automotive and general purpose power switching:
c
c
◆ 12 V and 24 V loads.
◆ Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT428 (D-PAK), simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
2 drain (d)
3 source (s)
mb drain (d)
1. TrenchMOS is a trademark of Royal Philips Electronics.
mb
2
13
Top view
SOT428 (D-PAK)
MBK091
g
MBB076
d
s
Philips Semiconductors
BUK9219-55A
TrenchMOS™ logic level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
V
I
P
T
R
DS
D
tot
j
DSon
drain-source voltage (DC) − 55 V
drain current (DC) Tmb=25°C; VGS=5V − 55 A
total power dissipation Tmb=25°C − 114 W
junction temperature − 175 °C
drain-source on-state resistance VGS=5V; ID= 25 A 15 19 mΩ
= 4.5 V; ID=25A − 20 mΩ
V
GS
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
DR
I
DRM
Avalanche ruggedness
W
DSS
drain-source voltage (DC) − 55 V
drain-gate voltage (DC) RGS=20kΩ−55 V
gate-source voltage (DC) −±10 V
non-repetitive gate-source voltage tp≤ 50 µs −±15 V
drain current (DC) Tmb=25°C; VGS=5V;Figure 2 and 3 − 55 A
= 100 °C; VGS=5V;Figure 2 − 38 A
T
mb
peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; Figure 3 [1] − 219 A
total power dissipation Tmb=25°C; Figure 1 − 114 W
storage temperature −55 +175 °C
operating junction temperature −55 +175 °C
reverse drain current (DC) Tmb=25°C − 55 A
pulsed reverse drain current Tmb=25°C; pulsed; tp≤ 10 µs − 219 A
non-repetitive avalanche energy unclamped inductive load; ID=49A;
≤ 55 V; VGS=5V; RGS=50Ω;
V
DS
starting T
=25°C
j
− 120 mJ
[1] IDM is limited by chip, not package.
9397 750 07642
Product specification Rev. 01 — 24 October 2000 2 of 13
© Philips Electronics N.V. 2000. All rights reserved.
Philips Semiconductors
BUK9219-55A
TrenchMOS™ logic level FET
120
P
der
(%)
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200
P
P
der
tot
----------------------
P
tot 25 C°()
100%×=
03aa16
Tmb (oC)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
1000
I
D
(A)
R
= VDS/ I
100
DSon
D
120
I
der
(%)
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200
03aa24
Tmb (oC)
VGS≥ 4.5 V
I
I
der
D
------------------ -
I
D25C°()
100%×=
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03nb64
tp =
10 us
100 us
t
P
10
t
p
1
1 10 100
p
δ =
T
t
T
D.C.
1 ms
10 ms
100 ms
VDS (V)
Tmb=25°C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 07642
© Philips Electronics N.V. 2000. All rights reserved.
Product specification Rev. 01 — 24 October 2000 3 of 13
Philips Semiconductors
BUK9219-55A
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Value Unit
R
th(j-a)
R
th(j-mb)
thermal resistance from junction to ambient minimum footprint, FR4 board 71.4 K/W
thermal resistance from junction to mounting
Figure 4 1.3 K/W
base
7.1 Transient thermal impedance
03nb65
t
p
δ =
T
T
tp (s)
t
1
t
p
-1
Z
th(j-mb)
(K/W)
0.01
0.001
0.1
10
1
δ = 0.5
0.2
0.1
0.05
0.02
Single Shot
-6
10
-5
10
-4
10
-3
10
-2
10
P
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 07642
© Philips Electronics N.V. 2000. All rights reserved.
Product specification Rev. 01 — 24 October 2000 4 of 13
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