Philips buk7621 30 DATASHEETS

Philips Semiconductors Product specification
TrenchMOS transistor BUK7621-30 Standard level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT standard level field-effect power transistor in a plastic envelope V suitable for surface mounting using I ’trench’ technology. The device P featuresverylow on-state resistance T and has integral zener diodes giving R
DS
D
tot j
DS(ON)
ESD protection up to 2kV. It is resistance VGS = 10 V intended for use in automotive and general purpose switching applications.

PINNING - SOT404 (D2PAK) PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
mb
d
1 gate 2 drain 3 source
mb drain
2
13
g
s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V V ±V I
D
I
D
I
DM
P T
DS DGR
tot
stg
GS
, T
j
Drain-source voltage - - 30 V Drain-gate voltage RGS = 20 k -30V Gate-source voltage - - 20 V Drain current (DC) Tmb = 25 ˚C - 50 A Drain current (DC) Tmb = 100 ˚C - 29 A Drain current (pulse peak value) Tmb = 25 ˚C - 200 A Total power dissipation Tmb = 25 ˚C - 94 W Storage & operating temperature - - 55 175 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 1.6 K/W mounting base
R
th j-a
Thermal resistance junction to pcb mounted, minimum 50 - K/W ambient footprint

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
July 1997 1 Rev 1.000
Electrostatic discharge capacitor Human body model - 2 kV voltage, all pins (100 pF, 1.5 k)
Philips Semiconductors Product specification
TrenchMOS transistor BUK7621-30
Standard level FET

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)

DYNAMIC CHARACTERISTICS

Tj = 25˚C unless otherwise specified
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V voltage Tj = -55˚C 27 - - V Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - V
Tj = -55˚C - - 4.4 V
Zero gate voltage drain current VDS = 30 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - - 20 µA Gate source breakdown voltage IG = ±1 mA; 16 - - V Drain-source on-state VGS = 10 V; ID = 25 A - 19 21 m resistance Tj = 175˚C - - 39 m
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g Q
Q Q
C C C
t t t t
L L
fs
g(tot) gs gd
iss oss rss
d on r d off f
d d
Forward transconductance VDS = 25 V; ID = 25 A 6 19 - S Total gate charge ID = 25 A; V
= 30 V; VGS = 10 V - 28 - nC
DD
Gate-source charge - 7 - nC Gate-drain (Miller) charge - 11 - nC
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 974 - pF Output capacitance - 325 - pF Feedback capacitance - 152 - pF
Turn-on delay time VDD = 30 V; ID = 25 A; - 10 - ns Turn-on rise time VGS = 10 V; RG = 10 -45-ns Turn-off delay time Resistive load - 30 - ns Turn-off fall time - 32 - ns
Internal drain inductance Measured from tab to centre of die - 3.5 - nH Internal drain inductance Measured from drain lead solder - 4.5 - nH
point to centre of die
L
s
Internal source inductance Measured from source lead solder - 7.5 - nH
point to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
t
rr
Q
SD
rr
Continuous reverse drain - - 50 A current Pulsed reverse drain current - - 200 A Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V
IF = 50 A; VGS = 0 V - 1.0 -
Reverse recovery time IF = 25 A; -dIF/dt = 100 A/µs; - 100 - ns Reverse recovery charge VGS = -10 V; VR = 25 V - 0.4 - µC
July 1997 2 Rev 1.000
Philips Semiconductors Product specification
TrenchMOS transistor BUK7621-30
Standard level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
Drain-source non-repetitive ID = 25 A; VDD 25 V; - - 70 mJ unclamped inductive turn-off VGS = 10 V; RGS = 50 ; Tmb = 25 ˚C energy
PD%
120 110 100
90 80 70 60 50 40 30 20 10
0
0 20 40 60 80 100 120 140 160 180
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
ID%
120 110 100
90 80 70 60 50 40 30 20 10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
= f(Tmb)
D 25 ˚C
Normalised Current Derating
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Tmb); conditions: VGS ≥ 5 V
D 25 ˚C
ID, Drain current (Amps)
1000
100
10
RDS(ON) = VDS/ID
DC
Tmb = 25 C
1
1 10 100
VDS, Drain-source voltage (Volts)
PHP50N03T
tp = 10 us
100 us
1 ms 10 ms
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
p
t
T
PHP50N03T
p
t
D =
T
t
Transient thermal impedance, Zth j-mb (K/W)
10
D =
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
1us 10us 100us 1ms 10ms 0.1s 1s 10s
pulse width, tp (s)
P
D
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-mb
p
July 1997 3 Rev 1.000
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