Philips BUK574-60H Datasheet
Philips Semiconductors Objective specification
PowerMOS transistor BUK574-60H
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in
a plastic full-pack envelope. V
The device is intended for use in I
Automotive applications, Switched P
Mode Power Supplies (SMPS), T
motor control, welding, DC/DC and R
DS
D
tot
j
DS(ON)
AC/DC converters, and in general resistance; VGS = 5 V
purpose switching applications.
PINNING - SOT186A PIN CONFIGURATION SYMBOL
Drain-source voltage 60 V
Drain current (DC) 20 A
Total power dissipation 30 W
Junction temperature 150 ˚C
Drain-source on-state 42 mΩ
PIN DESCRIPTION
case
d
1 gate
2 drain
g
3 source
case isolated
123
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
DGR
±VGSGate-source voltage - - 15 V
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
Drain-source voltage - - 60 V
Drain-gate voltage RGS = 20 kΩ -60V
Non-repetitive gate-source tp ≤ 50 µs - 20 V
voltage
Drain current (DC) Ths = 25 ˚C - 20 A
Drain current (DC) Ths = 100 ˚C - 13.5 A
Drain current (pulse peak value) Ths = 25 ˚C - 80 A
Total power dissipation Ths = 25 ˚C - 30 W
Storage temperature - - 55 150 ˚C
Junction Temperature - - 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-hs
R
th j-a
July 1996 1 Rev 1.001
Thermal resistance junction to With heatsink compound - 4.17 K/W
heatsink
Thermal resistance junction to 55 - K/W
ambient
Philips Semiconductors Objective specification
PowerMOS transistor BUK574-60H
Logic level FET
STATIC CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
DSS
I
GSS
R
DS(ON)
DYNAMIC CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
s
Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 - - V
voltage
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 25 ˚C - 1 10 µA
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj =125 ˚C - 0.1 1.0 mA
Gate source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA
Drain-source on-state VGS = 5 V; - 34 42 mΩ
resistance ID = 20 A
Forward transconductance VDS = 25 V; ID = 20 A 10 18 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1100 1750 pF
Output capacitance - 420 600 pF
Feedback capacitance - 160 275 pF
Turn-on delay time VDD = 30 V; ID = 3 A; - 25 40 ns
Turn-on rise time VGS = 5 V; RGS = 50 Ω; - 110 150 ns
Turn-off delay time R
= 50 Ω - 150 220 ns
gen
Turn-off fall time - 100 145 ns
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
isol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - 2500 V
three terminals to external waveform;
heatsink R.H. ≤ 65% ; clean and dustfree
C
isol
Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
SD
t
rr
Q
rr
July 1996 2 Rev 1.001
Continuous reverse drain - - - 20 A
current
Pulsed reverse drain current - - - 80 A
Diode forward voltage IF = 20 A ; VGS = 0 V - 0.9 2.0 V
Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 60 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 0.25 - µC
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