Philips BUK573-48C Datasheet
Philips Semiconductors Product specification
PowerMOS transistor BUK573-48C
Clamped logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
Protected N-channel enhancement SYMBOL PARAMETER MIN. TYP. MAX. UNIT
mode logic level field-effect power
transistor in a plastic full-pack V
envelope. I
The device is intended for use in P
automotive applications. It has W
(CL)DSR
D
tot
DSRR
built-inzenerdiodesproviding active energy; Tj = 150˚C
drain voltage clamping. R
DS(ON)
PINNING - SOT186A PIN CONFIGURATION SYMBOL
Drain-source clamp voltage 40 48 58 V
Drain current (DC) 13 A
Total power dissipation 25 W
Repetitive clamped turn off 50 mJ
Drain-source on-state 85 mΩ
resistance; VGS = 5 V
PIN DESCRIPTION
case
d
1 gate
2 drain
3 source
case isolated
123
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
±V
I
D
I
D
I
DM
P
T
T
DS
DG
GS
tot
stg
j
Drain-source voltage continuous - 30 V
Drain-gate voltage continuous - 30 V
Gate-source voltage - - 15 V
Drain current (DC) Ths = 25 ˚C - 13 A
Drain current (DC) Ths = 100 ˚C - 8.2 A
Drain current (pulse peak Ths = 25 ˚C - 52 A
value)
Total power dissipation Ths = 25 ˚C - 25 W
Storage temperature - - 55 150 ˚C
Junction Temperature - - 55 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-hs
R
th j-a
August 1994 1 Rev 1.000
Thermal resistance junction to with heatsink compound - - 5 K/W
heatsink
Thermal resistance junction to - 55 - K/W
ambient
Philips Semiconductors Product specification
PowerMOS transistor BUK573-48C
Clamped logic level FET
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DG
V
GS(TO)
V
GS(ON)
I
DSS
I
GSS
R
DS(ON)
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(CL)DSR
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
s
Drain-gate zener voltage 0.2 < -IG < 0.4 mA; 38 45 54 V
-55˚C < Tj < 150˚C
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Gate voltage VDS = 10 V; ID = 10 A; 2.0 3.1 4.0 V
-55˚C < Tj < 150˚C
Zero gate voltage drain current VDS = 30 V; VGS = 0 V; Tj =150 ˚C - 0.01 1.0 mA
Gate source leakage current VGS = ±15 V; VDS = 0 V; Tj =150 ˚C - 0.1 10 µA
Drain-source on-state VGS = 5 V; ID = 10 A - 65 85 mΩ
resistance
Drain source clamp voltage RG = 10 kΩ; ID = 10 A; 40 48 58 V
(peak value) -55 < Tj < 150˚C; Inductive load.
Forward transconductance VDS = 25 V; ID = 10 A 7 12 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 550 825 pF
Output capacitance - 240 350 pF
Feedback capacitance - 100 160 pF
Turn-on delay time VDD = 12 V; ID = 5 A; - 3.5 - µs
Turn-on rise time VGS = 5 V; RG = 10 kΩ; - 22 - µs
Turn-off delay time - 16 - µs
Turn-off fall time - 18 - µs
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
ISOLATION
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
isol(rms)
C
isol
August 1994 2 Rev 1.000
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal waveform; - - 2500 V
RMS
three terminals to external R.H. < 65 %; clean and dust free
heatsink
Capacitance from T2 to f = 1 MHz - 10 - pF
external heatsink
Philips Semiconductors Product specification
PowerMOS transistor BUK573-48C
Clamped logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
SD
CLAMPED ENERGY LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
W
DSRS
W
DSRR
Continuous reverse drain - - - 13 A
current
Pulsed reverse drain current - - - 52 A
Diode forward voltage IF = 13 A ; VGS = 0 V - 1.05 1.3 V
Drain-source non repetitive Tj = 25˚C prior to clamping; - 200 mJ
clamped inductive turn off ID = 10 A; VGS = 5 V; RGS = 10 kΩ;
energy inductive load (see Figs. 17,18)
Drain-source repetitive clamped Tj = 150˚C prior to clamping; - 50 mJ
inductive turn off energy ID = 10 A; VGS = 5 V; RGS = 10 kΩ;
inductive load (see Figs. 17,18)
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Normalised Power Derating
with heatsink compound
Ths / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
D 25 ˚C
= f(Ths)
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Normalised Current Derating
with heatsink compound
Ths / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Ths); conditions: VGS ≥ 5 V
D 25 ˚C
August 1994 3 Rev 1.000
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