Monolithic temperature andSYMBOLPARAMETERMAX.UNIT
overload protected logic level power
MOSFET in TOPFET2 technologyV
assembled in a 3 pin surface mount
plastic package.I
TrenchMOS output stage
Current limiting
Overload protection
Overtemperature protection
Protection latched reset by input
5 V logic compatible input level
Control of output stage and
supply of overload protection
circuits derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
INPUT
RIG
LOGIC AND
PROTECTION
O / V
CLAMP
DRAIN
POWER
MOSFET
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223PIN CONFIGURATIONSYMBOL
PINDESCRIPTION
1input
2drain
3source
4drain (tab)
1
October 19991Rev 1.000
4
23
TOPFET
I
D
P
S
Philips SemiconductorsProduct specification
PowerMOS transistorBUK127-50DL
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
I
I
I
P
T
T
DS
D
I
IRM
D
stg
j
Continuous drain source voltage
Continuous drain current
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOLPARAMETERREQUIRED CONDITIONMIN.MAX.UNIT
V
DDP
Protected drain source supply voltage VIS ≥ 4 V-35V
THERMAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Thermal resistance
R
R
R
th j-sp
th j-b
th j-a
Junction to solder point-1218K/W
Junction to board
4
Mounted on any PCB-40-K/W
Junction to ambientMounted on PCB of fig. 22--70K/W
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not in an overload condition with drain current limiting.
4 Temperature measured 1.3 mm from tab.
October 19992Rev 1.000
Philips SemiconductorsProduct specification
PowerMOS transistorBUK127-50DL
Logic level TOPFET
OUTPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Off-stateVIS = 0 V
V
(CL)DSS
Drain-source clamping voltageID = 10 mA50--V
ID = 200 mA; tp ≤ 300 µs; δ≤ 0.01506070V
I
DSS
Drain source leakage currentVDS = 40 V--100µA
Tmb = 25 ˚C-0.110µA
On-stateVIS ≥ 4 V; tp ≤ 300 µs; δ≤ 0.01
R
DS(ON)
Drain-source resistanceID = 100 mA--380mΩ
Tmb = 25 ˚C-150200mΩ
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
I
IS
I
ISL
V
t
lr
V
R
IS(TO)
ISR
(CL)IS
IG
Input threshold voltageVDS = 5 V; ID = 1 mA0.6-2.4V
Tmb = 25˚C1.11.62.1V
Input supply currentnormal operation; VIS = 5 V100220400µA
VIS = 4 V80195330µA
Input supply currentprotection latched; VIS = 5 V200400650µA
VIS = 3 V130250430µA
Protection reset voltage
Latch reset timeV
1
reset time tr ≥ 100 µs1.522.5V
= 5 V, V
IS1
< 1 V1040100µs
IS2
Input clamping voltageII = 1.5 mA5.5-8.5V
Input series resistance
2
Tmb = 25˚C-33-kΩ
to gate of power MOSFET
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
October 19993Rev 1.000
Philips SemiconductorsProduct specification
PowerMOS transistorBUK127-50DL
Logic level TOPFET
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when one of the overload thresholds is exceeded.
It remains latched off until reset by the input.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Overload protection-40˚C ≤ Tj ≤ 150˚C
I
D
Drain current limitingVIS = 5 V0.81.31.7A
VIS = 4.5 V0.7--A
VIS = 4 V to 5.5 V0.6-1.8A
Short circuit load protectionVIS = 5 V
P
T
D(TO)
DSC
Overload power thresholdfor protection to operate-17-W
Characteristic timewhich determines trip time
1
-1.6-ms
Overtemperature protectionfrom ID ≥ 280 mA or VDS ≥ 100 mV
T
j(TO)
Threshold junction temperature VIS = 4 V to 5.5 V150165-˚C
SWITCHING CHARACTERISTICS
Ta = 25˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
t
t
t
t
d on
r
d off
f
Turn-on delay timeVIS: 0 V ⇒ 5 V-512µs
Rise time-1130µs
Turn-off delay timeVIS: 5 V ⇒ 0 V-2565µs
Fall time-1435µs
REVERSE DIODE LIMITING VALUE
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
I
S
Continuous forward currentTmb ≤ 25 ˚C; VIS = 0 V-2A
REVERSE DIODE CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
SDO
t
rr
1 Trip time t
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.