Philips BUK106-50SP, BUK106-50S, BUK106-50LP, BUK106-50L Datasheet

Philips Semiconductors Product specification

PowerMOS transistor BUK106-50L/S
Logic level TOPFET BUK106-50LP/SP

DESCRIPTION QUICK REFERENCE DATA

Monolithic temperature and SYMBOL PARAMETER MAX. UNIT
overload protected logic level power
MOSFET in a 5 pin plastic V

DS

Continuous drain source voltage 50 V

envelope, intended as a general I

D

Continuous drain current 50 A

purpose switch for automotive P

tot

Total power dissipation 125 W

systems and other applications. T

j

Continuous junction temperature 150 ˚C

R

DS(ON)

Drain-source on-state resistance

APPLICATIONS V

IS

= 5 V 35 mΩ

VIS = 8 V 28 mΩ

General controller for driving

lamps SYMBOL PARAMETER NOM. UNIT
motors
solenoids V

PSN

Protection supply voltage

heaters BUK106-50L 5V

BUK106-50S 10 V

FEATURES FUNCTIONAL BLOCK DIAGRAM

Vertical power DMOS output
stage
Low on-state resistance
Logic and protection supply
from separate pin
Low operating supply current
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
5 V logic compatible input level
Separate input pin
for higher frequency drive
ESD protection on input, flag
and protection supply pins
Over voltage clamping for turn
off of inductive loads
Both linear and switching
operation are possible Fig.1. Elements of the TOPFET.

PINNING - SOT263 PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 input
2 flag
3 drain
4 protection supply
5 source

Fig. 2. Type numbers ending with

suffix P refer to leadform 263-01. Fig. 3.

tab drain

POWER
MOSFET

DRAIN

SOURCE

INPUT

O/V

CLAMP

LOGIC AND

PROTECTION

PROTECTION SUPPLY

FLAG

leadform

tab

12345

263-01

D

S

I

TOPFET

P

F

P

February 1993 1 Rev 1.200

Philips Semiconductors Product specification

PowerMOS transistor BUK106-50L/S
Logic level TOPFET BUK106-50LP/SP

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Voltages

V

DSS

Continuous off-state drain source VIS = 0 V - 50 V
voltage

1

V

IS

Continuous input voltage - 0 11 V

V

FS

Continuous flag voltage - 0 11 V

V

PS

Continuous supply voltage - 0 11 V
Currents VIS = - 8 5 V

I

D

Continuous drain current T

mb ≤

25 ˚C - 50 45 A

I

D

Continuous drain current T

mb ≤

100 ˚C - 31 28 A

I

DRM

Repetitive peak on-state drain current Tmb ≤ 25 ˚C - 200 180 A

Thermal

P

tot

Total power dissipation Tmb = 25 ˚C - 125 W

T

stg

Storage temperature - -55 150 ˚C

T

j

Junction temperature

2

continuous - 150 ˚C

T

sold

Lead temperature during soldering - 250 ˚C

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply An n-MOS transistor turns on For internal overload protection to
connected, TOPFET can protect between the input and source to remain latched while the control
itself from two types of overload - quickly discharge the power circuit is high, external series input
over temperature and short circuit MOSFET gate capacitance. resistance must be provided. Refer
load. to INPUT CHARACTERISTICS.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VIS =85 - V

V

PSP

Protection supply voltage

3

for valid protection

BUK106-50L 4.4 4 - V
BUK106-50S 5.4 5 - V

Over temperature protection VPS = V

PSN

V

DDP(T)

Protected drain source supply voltage VIS = 10 V; RI ≥ 2 kΩ -50V

V

IS

= 5 V; RI ≥ 1 kΩ -50V

Short circuit load protection VPS = V

PSN

; L ≤ 10 µH

V

DDP(P)

Protected drain source supply voltage4VIS = 10 V; RI ≥ 2 kΩ -24V

V

IS

= 5 V; RI ≥ 1 kΩ -45V

P

DSM

Instantaneous overload dissipation - 4 kW

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold T

j(TO)

the over temperature trip operates to protect the switch.

3 The minimum supply voltage required for correct operation of the overload protection circuits.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed V

DDP(P)

maximum.

For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

February 1993 2 Rev 1.200

Philips Semiconductors Product specification

PowerMOS transistor BUK106-50L/S
Logic level TOPFET BUK106-50LP/SP

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

I

DRRM

Repetitive peak clamping drain current RIS ≥ 100 Ω

1

-50A

E

DSM

Non-repetitive inductive turn-off IDM = 27 A; RIS ≥ 100 Ω -1J
energy

2

E

DRM

Repetitive inductive turn-off energy RIS ≥ 100 Ω; Tmb ≤ 85 ˚C; - 80 mJ

IDM = 16 A; VDD ≤ 20 V;
f = 250 Hz

I

DIRM

Repetitive peak drain to input current3RIS = 0 Ω; tp ≤ 1 ms - 50 mA

REVERSE DIODE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

I

S

Continuous forward current Tmb = 25 ˚C; - 50 A

VIS = VPS = VFS = 0 V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Thermal resistance

R

th j-mb

Junction to mounting base - - 0.8 1.0 K/W

R

th j-a

Junction to ambient in free air - 60 - K/W

STATIC CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(CL)DSR

Drain-source clamping voltage RIS = 100 Ω; ID = 10 mA 50 - 65 V

V

(CL)DSR

Drain-source clamping voltage RIS = 100 Ω; IDM = 1 A; tp ≤ 300 µs; 50 - 70 V

δ ≤ 0.01

I

DSS

Zero input voltage drain current VDS = 12 V; VIS = 0 V - 0.5 10 µA

I

DSR

Drain source leakage current VDS = 50 V; RIS = 100 Ω;-120µA

I

DSR

Drain source leakage current VDS = 40 V; RIS = 100 Ω;

Tj = 125 ˚C - 10 100 µA

R

DS(ON)

Drain-source on-state IDM = 25 A; VIS = 8 V - 22 28 mΩ
resistance tp ≤ 300 µs; δ ≤ 0.01 VIS = 5 V - 28 35 mΩ

1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to

become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS.

2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at

energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS.

3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source

voltage becoming positive.

February 1993 3 Rev 1.200

Philips Semiconductors Product specification

PowerMOS transistor BUK106-50L/S
Logic level TOPFET BUK106-50LP/SP

OVERLOAD PROTECTION CHARACTERISTICS

With adequate protection supply Provided there is adequate input Refer also to OVERLOAD
voltage TOPFET detects when one series resistance it switches off PROTECTION LIMITING VALUES
of the overload thresholds is and remains latched off until reset and INPUT CHARACTERISTICS.
exceeded. by the protection supply pin.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Short circuit load protection1VPS = V

PSN

2

; Tmb = 25 ˚C; L ≤ 10 µH

E

DS(TO)

Overload threshold energy VDD = 13 V; VIS = 10 V - 550 - mJ

t

d sc

Response time VDD = 13 V; VIS = 10 V - 0.4 - ms
Over temperature protection VPS = V

PSN

T

j(TO)

Threshold junction temperature from ID ≥ 2.5 A

3

150 - - ˚C

TRANSFER CHARACTERISTICS

Tmb = 25 ˚C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g

fs

Forward transconductance VDS = 12 V; IDM = 25 A tp ≤ 300 µs; 17 28 - S

δ ≤ 0.01

I

D

Drain current

4

VDS = 13 V; VIS = 5 V - 80 - A

VIS = 10 V 160 - A

PROTECTION SUPPLY CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Protection supply

IPS, Protection supply current normal operation or
I

PSL

protection latched

BUK106-50L VPS = 5 V - 0.2 0.35 mA
BUK106-50S VPS = 10 V - 0.4 1.0 mA

V

PSR

Protection reset voltage

5

1.5 2.5 3.5 V

Tj = 150 ˚C 1.0 - - V

V

(CL)PS

Protection clamp voltage IP = 1.35 mA 11 13 - V

REVERSE DIODE CHARACTERISTICS

Tmb = 25 ˚C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

SDS

Forward voltage IS = 20 A; VIS = VPS = VFS = 0 V; - 0.9 1.2 V

tp = 300 µs

t

rr

Reverse recovery time not applicable

6

----

1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for

P

DSM

, which is always the case when VDS is less than V

DSP

maximum.

2 At the appropriate nominal protection supply voltage for each type. Refer to QUICK REFERENCE DATA.
3 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum I

D

ensures this condition.

4 During overload condition. Refer also to OVERLOAD PROTECTION LIMITING VALUES and CHARACTERISTICS.
5 The supply voltage below which the overload protection circuits will be reset.
6 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

February 1993 4 Rev 1.200

Philips Semiconductors Product specification

PowerMOS transistor BUK106-50L/S
Logic level TOPFET BUK106-50LP/SP

INPUT CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Normal operation

V

IS(TO)

Input threshold voltage VDS = 5 V; ID = 1 mA 1.0 1.5 2.0 V

Tmb = 150 ˚C 0.5 - - V

I

IS

Input current VIS = 10 V - 10 100 nA

V

(CL)IS

Input clamp voltage II = 1 mA 11 13 - V

Overload protection latched

R

ISL

Input resistance

1

VPS = 5 V II = 5 mA; - 55 - Ω

Tmb = 150 ˚C - 95 - Ω

VPS = 10 V II = 5 mA; - 35 - Ω

Tmb = 150 ˚C - 60 - Ω

Application information

External input resistances for (see figure 29)

R

IS

internal overvoltage clamping2RI = ∞ Ω;V

DS

> 30 V 100 - - Ω

R

I

internal overload protection

3

RIS = ∞ Ω;V

II

= 5 V 1 - - kΩ

VII = 10 V 2 - - kΩ

SWITCHING CHARACTERISTICS

Tmb = 25 ˚C; RI = 50 Ω; RIS = 50 Ω (see figure 29); resistive load RL = 10 Ω. For waveforms see figure 28.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

d on

Turn-on delay time VDD = 15 V; VIS: 0 V ⇒ 10 V - 10 - ns

t

r

Rise time - 35 - ns

t

d off

Turn-off delay time VDD = 15 V; VIS: 10 V ⇒ 0 V - 280 - ns

t

f

Fall time - 120 - ns

CAPACITANCES

Tmb = 25 ˚C; f = 1 MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C

iss

Input capacitance VDS = 25 V; VIS = 0 V - 1250 1800 pF

C

oss

Output capacitance VDS = 25 V; VIS = 0 V - 650 1000 pF

C

rss

Reverse transfer capacitance VDS = 25 V; VIS = 0 V - 150 250 pF

C

pso

Protection supply pin VPS = 10 V - 30 - pF
capacitance

C

fso

Flag pin capacitance VFS = 10 V; VPS = 0 V - 20 - pF

1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.

The external drive circuit should be such that the input voltage does not exceed V

IS(TO)

minimum when the overload protection has

operated. Refer also to figure for latched input characteristics.

2 Applications using a lower value for RIS would require external overvoltage protection.
3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to

switch off the input.

February 1993 5 Rev 1.200