Philips BT136S E Technical data
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Philips Semiconductors Product specification
Triacs BT136S series E
sensitive gate
GENERAL DESCRIPTION QUICK REFERENCE DATA
Passivated, sensitive gate triacs in a SYMBOL PARAMETER MAX. MAX. UNIT
plastic envelope, suitable for surface
mounting, intended for use in general BT136S- 600E 800E
purpose bidirectional switching and V
DRM
phase control applications, where voltages
high sensitivity is required in all four I
quadrants. I
T(RMS)
TSM
PINNING - SOT428 PIN CONFIGURATION SYMBOL
Repetitive peak off-state 600 800 V
RMS on-state current 4 4 A
Non-repetitive peak on-state 25 25 A
current
PIN DESCRIPTION
1 MT1
tab
T1T2
2 MT2
3 gate
tab MT2
2
1
3
G
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
-600 -800
V
DRM
I
T(RMS)
I
TSM
Repetitive peak off-state - 600
voltages
RMS on-state current full sine wave; Tmb ≤ 107 ˚C - 4 A
Non-repetitive peak full sine wave; Tj = 25 ˚C prior to
on-state current surge
t = 20 ms - 25 A
I2tI
2
t for fusing t = 10 ms - 3.1 A2s
t = 16.7 ms - 27 A
dIT/dt Repetitive rate of rise of ITM = 6 A; IG = 0.2 A;
on-state current after dIG/dt = 0.2 A/µs
triggering T2+ G+ - 50 A/µs
I
V
P
P
T
T
GM
GM
GM
G(AV)
stg
j
Peak gate current - 2 A
Peak gate voltage - 5 V
Peak gate power - 5 W
Average gate power over any 20 ms period - 0.5 W
Storage temperature -40 150 ˚C
Operating junction - 125 ˚C
temperature
T2+ G- - 50 A/µs
T2- G- - 50 A/µs
T2- G+ - 10 A/µs
1
800 V
1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may
switch to the on-state. The rate of rise of current should not exceed 3 A/µs.
June 2001 1 Rev 1.200
Philips Semiconductors Product specification
Triacs BT136S series E
sensitive gate
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
R
th j-a
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
GT
I
L
I
H
V
T
V
GT
I
D
Thermal resistance full cycle - - 3.0 K/W
junction to mounting base half cycle - - 3.7 K/W
Thermal resistance pcb (FR4) mounted; footprint as in Fig.14 - 75 - K/W
junction to ambient
Gate trigger current VD = 12 V; IT = 0.1 A
T2+ G+ - 2.5 10 mA
T2+ G- - 4.0 10 mA
T2- G- - 5.0 10 mA
T2- G+ - 11 25 mA
Latching current VD = 12 V; IGT = 0.1 A
T2+ G+ - 3.0 15 mA
T2+ G- - 10 20 mA
T2- G- - 2.5 15 mA
T2- G+ - 4.0 20 mA
Holding current VD = 12 V; IGT = 0.1 A - 2.2 15 mA
On-state voltage IT = 5 A - 1.4 1.70 V
Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.7 1.5 V
VD = 400 V; IT = 0.1 A; Tj = 125 ˚C 0.25 0.4 - V
Off-state leakage current VD = V
; Tj = 125 ˚C - 0.1 0.5 mA
DRM(max)
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
dVD/dt Critical rate of rise of VDM = 67% V
off-state voltage exponential waveform; gate open circuit
t
gt
Gate controlled turn-on ITM = 6 A; VD = V
time dIG/dt = 5 A/µs
; Tj = 125 ˚C; - 50 - V/µs
DRM(max)
; IG = 0.1 A; - 2 - µs
DRM(max)
June 2001 2 Rev 1.200
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