Philips BST86 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BST86
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in SOT89
envelope and designed for use as
Surface Mounted Device (SMD) in
thin and thick-film circuits for
application with relay, high-speed and
line-transformer drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No second breakdown
QUICK REFERENCE DATA
Drain-source voltage V
Drain-source voltage (non-repetitive peak;
≤ 2 ms)
t
p
Gate-source voltage (open drain) ±V
Drain current (DC) I
Total power dissipation up to T
Drain-source ON-resistance
ID= 15 mA; VGS=3 V R
Transfer admittance
= 300 mA; VDS= 15 V Yfs typ. 250 mS
I
D
PINNING - SOT89
1 = source
2 = drain
3 = gate
=25°CP
amb
DS
V
DS(SM)
D
tot
DS(on)
GSO
BST86
max. 180 V
max. 200 V
max. 20 V
max. 300 mA
max. 1 W
typ.
max.
710Ω
Ω
PIN CONFIGURATION
Marking: K0
handbook, halfpage
Bottom view
Fig.1 Simplified outline and symbol.
123
d
g
s
MAM355
April 1995 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
Drain-source voltage (non-repetitive peak; t
≤ 2 ms) V
p
Gate-source voltage (open drain)
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T
= 25 °C (note 1) P
amb
Storage temperature range T
Junction temperature T
THERMAL RESISTANCE
From junction to ambient (note 1) R
Note
2
1. Transistor mounted on a ceramic substrate of 2.5 cm
and thickness of 0.7 mm.
DS
DS(SM)
±VGSO
D
DM
tot
stg
j
th j-a
BST86
max. 180 V
max. 200 V
max. 20 V
max. 300 mA
max. 800 mA
max. 1 W
−65 to + 150 °C
max. 150 °C
= 125 K/W
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
=25°C unless otherwise specified
j
Drain-source breakdown voltage
I
= 100 µA; VGS=0 V
D
(BR)DSS
Drain-source leakage current
VDS= 120 V; VGS=0 I
DSS
Gate-source leakage current
VGS= 20 V; VDS=0 I
GSS
Gate threshold voltage
ID= 100 µA; VDS=V
GS
V
GS(th)
Drain-source ON-resistance
= 15 mA; VGS=3 V R
I
D
ID= 300 mA; VGS= 10 V R
DS(on)
DS(on)
Transfer admittance
I
= 300 mA; VDS= 15 V Yfs typ. 250 mS
D
Input capacitance at f = 1 MHz
V
= 10 V; VGS=0 C
DS
iss
Output capacitance at f = 1 MHz
VDS= 10 V; VGS=0 C
oss
Feedback capacitance at f = 1 MHz
VDS= 10 V; VGS= 0 C
rss
Switching times (see as 2 and 3)
ID= 300 mA; VDD= 50 V; VGS= 0 to 10 V t
on
t
off
min. 180 V
max. 10 µA
max. 100 nA
min.
max.
typ.
max.
typ. 6 Ω
typ.
max.
typ.
max.
typ.
max.
max.
max.
BST86
0.7
2.7VV
710Ω
Ω
5065pF
pF
2030pF
pF
610pF
pF
1015ns
ns
April 1995 4
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