Philips BST84 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BST84
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel vertical D-MOS transistor
in SOT89 envelope and designed for
use as line current interrupter in
telephone sets and for application in
relay, high-speed and
line-transformer drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No second breakdown
QUICK REFERENCE DATA
Drain-source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Total power dissipation up to T
Drain-source ON-resistance
ID= 250 mA; VGS= 10 V R
Transfer admittance
I
= 250 mA; VDS= 15 V Yfs typ. 250 mS
D
PINNING - SOT89
1 = source
2 = gate
3 = drain
=25°CP
amb
DS
GSO
D
tot
DS(on)
BST84
max. 200 V
max. 20 V
max. 250 mA
max. 1 W
typ.
max.
612Ω
Ω
PIN CONFIGURATION
handbook, 2 columns
g
MBB076 - 1
Marking: KN
handbook, halfpage
d
s
132
Bottom view
MSB013
Fig.1 Simplified outline and symbol.
April 1995 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T
= 25 °C (note 1) P
amb
Storage temperature range T
Junction temperature T
THERMAL RESISTANCE
From junction to ambient (note 1) R
Note
1. Transistor mounted on a ceramic substrate with area of 2.5 cm
DS
GSO
D
DM
tot
stg
j
th j-a
2
and thickness of 0.7 mm.
BST84
max. 200 V
max. 20 V
max. 250 mA
max. 800 mA
max. 1 W
−65 to + 150 °C
max. 150 °C
= 125 K/W
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
=25°C unless otherwise specified
j
Drain-source breakdown voltage
I
= 100 µA; VGS=0 V
D
(BR)DSS
Drain-source leakage current
VDS= 160 V; VGS=0 I
DSS
Gate-source leakage current
VGS= 20 V; VDS=0 I
GSS
Gate threshold voltage
ID= 1 mA; VDS=V
GS
V
GS(th)
Drain-source ON-resistance
= 250 mA; VGS= 10 V R
I
D
DS(on)
Transfer admittance
I
= 250 mA; VDS= 15 V Yfs typ. 250 mS
D
Input capacitance at f = 1 MHz
V
= 10 V; VGS=0 C
DS
iss
Output capacitance at f = 1 MHz
VDS= 10 V; VGS=0 C
oss
Feedback capacitance at f = 1 MHz
V
= 10 V; VGS= 0 C
DS
rss
Switching times (see Figs 2 and 3)
= 250 mA; VDD= 50 V; VGS= 0 to 10 V t
I
D
on
min. 200 V
max. 10 µA
max. 100 nA
min.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
BST84
0.8
2.8VV
612Ω
Ω
7090pF
pF
2030pF
pF
510pF
pF
410ns
ns
April 1995 4
t
off
typ.
max.
1525ns
ns
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