Philips BST76A Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BST76A
N-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of April 1995
File under Discrete Semiconductors, SC13b
1997 Jun 20
Philips Semiconductors Product specification
N-channel enhancement mode
vertical D-MOS transistor
FEATURES
• Direct interface to C-MOS, TTL, etc.
• High-speed switching
• No secondary breakdown.
APPLICATIONS
• Line current interrupter in telephone sets
• Relay, high-speed and line transformer drivers.
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor
in a SOT54 (TO-92) variant package.
PINNING - SOT54 (TO-92) variant
PIN SYMBOL DESCRIPTION
1 s source
2 g gate
3 d drain
handbook, halfpage
1
2
3
g
MAM146
Fig.1 Simplified outline and symbol.
BST76A
d
s
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
V
DS
V
DS(SM)
V
GSO
I
D
P
tot
R
DSon
y
forward transfer admittance ID= 300 mA; VDS= 15 V 250 − mS
fs
drain-source voltage (DC) − 180 V
drain-source voltage non-repetitive peak; tp≤ 2mS − 200 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) − 300 mA
total power dissipation T
≤ 25 °C − 1W
amb
drain-source on-state resistance ID= 15 mA; VGS=3V 7 10 Ω
1997 Jun 20 2
Philips Semiconductors Product specification
N-channel enhancement mode
BST76A
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
DS(SM)
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
Note to the Limiting values and Thermal characteristics
1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for drain lead minimum
10 mm × 10 mm.
drain-source voltage (DC) − 180 V
drain-source voltage non-repetitive peak; tp≤ 2mS − 200 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) − 300 mA
peak drain current − 800 mA
total power dissipation T
≤ 25 °C; note 1 − 1W
amb
storage temperature −65 +150 °C
junction temperature − 150 °C
thermal resistance from junction to ambient note 1 125 K/W
CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
forward transfer admittance ID= 300 mA; VDS=15V − 250 − mS
y
fs
C
iss
C
oss
C
rss
drain-source breakdown voltage VGS= 0; ID= 100 µA 180 −−V
gate-source threshold voltage VDS=VGS; ID= 100 µA 0.7 − 2.4 V
drain-source leakage current VDS= 120 V; VGS=0 −−10 µA
gate leakage current VDS= 0; VGS= ±20 V −−±100 nA
drain-source on-state resistance VGS=3V; ID=15mA − 710Ω
V
= 10 V; ID= 300 mA − 6 −Ω
GS
input capacitance VDS=10V; VGS= 0; f = 1 MHz − 50 65 pF
output capacitance VDS=10V; VGS= 0; f = 1 MHz − 20 30 pF
reverse transfer capacitance VDS=10V; VGS= 0; f = 1 MHz − 610pF
Switching times (see Figs 2 and 3)
t
on
turn-on time VGS= 0 to 10 V; VDS=50V;
−−10 ns
ID= 300 mA
t
off
turn-off time VGS=10to0V; VDS=50V;
−−15 ns
ID= 300 mA
1997 Jun 20 3
Philips Semiconductors Product specification
N-channel enhancement mode
vertical D-MOS transistor
handbook, halfpage
10 V
0 V
50 Ω
V = 50 V
DD
I
D
MSA631
handbook, halfpage
INPUT
OUTPUT
10 %
t
on
90 %
90 %
BST76A
10 %
t
off
MBB692
1.2
handbook, halfpage
P
tot
(W)
0.8
0.4
0
0 200
Fig.2 Switching times test circuit.
MLC697
50 100 150
T ( C)
amb
Fig.3 Input and output waveforms.
120
handbook, halfpage
C
(pF)
80
40
0
0
o
VGS= 0; f= 1 MHz; Tj=25°C.
(1) C
.
iss
(2) C
.
oss
(3) C
.
rss
10 20 30
MDA168
(1)
(2)
(3)
VDS (V)
Fig.4 Power derating curve.
1997 Jun 20 4
Fig.5 Capacitance as a function of drain-source
voltage; typical values.
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