Philips bst74a DATASHEETS
DISCRETE SEMICONDUCTORS
DATA SH EET
BST74A
N-channel vertical D-MOS
transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel vertical D-MOS transistor BST74A
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in TO-92
variant envelope and designed for
use as line current interrupter in
telephone sets and for application in
relay, high-speed and
line-transformer drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No second breakdown
PIN CONFIGURATION
QUICK REFERENCE DATA
Drain-source voltage V
Gate-source voltage (open drain) V
Drain current (DC) I
Total power dissipation up to T
=25°CP
amb
DS
GSO
D
tot
max. 200 V
max. 20 V
max. 250 mA
max. 1 W
Drain-source ON-resistance
ID= 250 mA; VGS= 10 V R
DS(on)
typ.
max.
Transfer admittance
I
= 250 mA; VDS= 15 V Yfs typ. 250 mS
D
PINNING - TO-92 VARIANT
1 = source
2 = gate
3 = drain
612Ω
Ω
handbook, halfpage
Note: Various pinout configurations available.
1
2
3
g
MAM146
Fig.1 Simplified outline and symbol.
d
s
April 1995 2
Philips Semiconductors Product specification
N-channel vertical D-MOS transistor BST74A
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
Gate-source voltage (open drain) V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T
=25°C (note 1) P
amb
Storage temperature range T
Junction temperature T
THERMAL RESISTANCE
DS
GSO
D
DM
tot
stg
j
max. 200 V
max. 20 V
max. 250 mA
max. 800 mA
max. 1 W
−65 to +150 °C
max. 150 °C
From junction to ambient (note 1) R
th j-a
= 125 K/W
Note
1. Transistor mounted on printed circuit board, max. lead length 4 mm, mounting pad for collector lead min.
10 mm× 10 mm.
April 1995 3
Philips Semiconductors Product specification
N-channel vertical D-MOS transistor BST74A
CHARACTERISTICS
T
=25°C unless otherwise specified
j
Drain-source breakdown voltage
I
=10µA; VGS=0 V
D
Drain-source leakage current
VDS= 160 V; VGS=0 I
Gate-source leakage current
VGS= 20 V; VDS=0 I
Gate threshold voltage
ID= 1 mA; VDS= V
GS
(BR)DS
DSS
GSS
V
GS(th)
min. 200 V
max. 10 µA
max. 100 nA
min.
max.
0.8
2.8VV
Drain-source ON-resistance (see Fig.4)
= 250 mA; VGS= 10 V R
I
D
DS(on)
typ.
max.
Transfer admittance
I
= 250 mA; VDS= 15 V Yfs typ. 250 mS
D
Input capacitance at f = 1 MHz
V
= 10 V; VGS=0 C
DS
iss
typ.
max.
Output capacitance at f = 1 MHz
= 10 V; VGS=0 C
V
DS
oss
typ.
max.
Feedback capacitance at f = 1 MHz
= 10 V; VGS=0 C
V
DS
rss
typ.
max.
Switching times (see Figs 2 and 3)
I
= 250 mA; VDS= 50 V; VGS= 0 to 10 V t
D
on
typ. 4 ns
max. 10 ns
t
off
typ. 15 ns
max. 25 ns
612Ω
Ω
7090pF
pF
2030pF
pF
510pF
pF
April 1995 4
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