Philips BST122 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BST122

P-channel enhancement mode
vertical D-MOS transistor

Product specification
File under Discrete Semiconductors, SC13b

April 1995

Philips Semiconductors Product specification

P-channel enhancement mode vertical
D-MOS transistor

DESCRIPTION

P-channel vertical D-MOS transistor
in SOT89 envelope and intended for
use in relay, high-speed and
line-transformer drivers, using
SMD-technology.

FEATURES

• Very low R

DS(on)

• Direct interface to C-MOS, TTL

• High-speed switching

• No second breakdown

QUICK REFERENCE DATA

Drain-source voltage −V
Gate-source voltage (open drain) ±V
Drain current (DC) −I
Total power dissipation up to T
Drain-source ON-resistance

−ID= 200 mA; −VGS= 10 V R

Transfer admittance

−I

= 200 mA; −VDS= 15 V  Yfs typ. 125 mS

D

PINNING - SOT89

1 = source
2 = drain
3 = gate

=25°CP

amb

DS
GSO

D

tot

DS(on)

BST122

max. 60 V
max. 20 V
max. 0,25 A
max. 1 W

max.
typ.

10

7.5ΩΩ

PIN CONFIGURATION

Marking: LN

handbook, halfpage

Bottom view

Fig.1 Simplified outline and symbol.

123

d

g

s

MAM354

April 1995 2

Philips Semiconductors Product specification

P-channel enhancement mode vertical
D-MOS transistor

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Drain-source voltage −V
Gate-source voltage (open drain) ±V
Drain current (DC) −I
Drain current (peak) −I
Total power dissipation up to T

= 25 °CP

amb

Storage temperature range T
Junction temperature T

THERMAL RESISTANCE

From junction to ambient (note 1) R

Note

1. Transistor mounted on a ceramic substrate: area = 2,5 cm

DS

GSO
D
DM

tot
stg
j

th j-a

2

; thickness = 0,7 mm.

BST122

max. 60 V
max. 20 V
max. 0.25 A
max. 0.5 A
max. 1 W

−65 to + 150 °C

max. 150 °C

= 125 K/W

April 1995 3

Philips Semiconductors Product specification

P-channel enhancement mode vertical
D-MOS transistor

CHARACTERISTICS

T

=25°C unless otherwise specified

j

Drain-source breakdown voltage

−I

=10µA; VGS=0 −V

D

(BR)DSS

Drain-source leakage current

−VDS= 48 V; VGS=0 −I

DSS

Gate-source leakage current

−VGS= 20 V; VDS=0 −I

GSS

Gate threshold voltage

−ID= 1 mA; VDS=V

GS

−V

GS(th)

Drain-source ON-resistance

−I

= 200 mA; −VGS= 10 V R

D

DS(on)

Transfer admittance

−I

= 200 mA; −VDS= 15 V  Yfs typ. 125 mS

D

Input capacitance at f = 1 MHz

−V

= 10 V; VGS=0 C

DS

iss

min. 60 V

max. 1 µA

max. 100 nA

min. 1.5 V
max. 3.5 V

max.
typ.

typ.
max.

BST122

10

7.5ΩΩ

3045pF

pF

Output capacitance at f = 1 MHz

= 10 V; VGS=0 C

−V

DS

Feedback capacitance at f = 1 MHz

= 10 V; VGS= 0 C

−V

DS

Switching times (see Figs 2 and 3)

−ID= 200 mA; −VDD= 50 V; −VGS= 0 to 10 V

oss

rss

t

on

t

off

typ.
max.

typ.
max.

typ.
typ.

2030pF

pF

510pF

pF

410ns

ns

April 1995 4