Philips BSS84 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSS84

P-channel enhancement mode
vertical D-MOS transistor

Product specification
Supersedes data of 1995 Apr 07
File under Discrete Semiconductors, SC13b

1997 Jun 18

Philips Semiconductors Product specification

P-channel enhancement mode
vertical D-MOS transistor

FEATURES

• Low threshold voltage

• Direct interface to C-MOS, TTL, etc.

• High-speed switching

• No secondary breakdown.

APPLICATIONS

• Line current interrupter in telephone sets

• Relay, high speed and line transformer drivers.

DESCRIPTION

P-channel enhancement mode vertical D-MOS transistor
in a SOT23 SMD package.

CAUTION

The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.

PINNING - SOT23

PIN SYMBOL DESCRIPTION

1 g gate
2 s source
3 d drain

handbook, halfpage

Top view

Marking code: SP

3

g

21

MAM188

Fig.1 Simplified outline and symbol.

BSS84

d

s

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

GSO

V

GSth

I

D

R

DSon

P

tot

drain-source voltage (DC) −−50 V
gate-source voltage (DC) open drain −±20 V
gate-source threshold voltage ID= −1 mA; VDS=V

GS

−0.8 −2V
drain current (DC) −−130 mA
drain-source on-state resistance ID= −130 mA; VGS= −10 V − 10 Ω
total power dissipation T

≤ 25 °C − 250 mW

amb

1997 Jun 18 2

Philips Semiconductors Product specification

P-channel enhancement mode

BSS84

vertical D-MOS transistor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

GSO

I

D

I

DM

P

tot

T

stg

T

j

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

Note to the Limiting values and Thermal characteristics

1. Device mounted on a printed-circuit board.

drain-source voltage (DC) −−50 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) −−130 mA
peak drain current −−520 mA
total power dissipation T

≤ 25 °C; note 1 − 250 mW

amb

storage temperature −65 +150 °C
operating junction temperature − 150 °C

thermal resistance from junction to ambient note 1 500 K/W

CHARACTERISTICS

=25°C unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GSth

I

DSS

I

GSS

R

DSon

 forward transfer admittance VDS= −25 V; ID= −130 mA 50 −−mS

y

fs

C

iss

C

oss

C

rss

drain-source breakdown voltage VGS= 0; ID= −10 µA −50 −−V
gate-source threshold voltage VDS=VGS; ID= −1mA −0.8 −−2V
drain-source leakage current VGS= 0; VDS= −40 V −−−100 nA

= 0; VDS= −50 V −−−10 µA

V

GS

V

= 0; VDS= −50 V; Tj= 125 °C −−−60 µA

GS

gate leakage current VDS= 0; VGS= ±20 V −−±10 nA
drain-source on-state resistance VGS= −10 V; ID= −130 mA −−10 Ω

input capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 25 45 pF
output capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 15 25 pF
reverse transfer capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 3.5 12 pF

Switching times (see Figs 2 and 3)
t

on

turn-on time VGS=0to−10 V; VDD= −40 V;

− 3 − ns

ID= −200 mA

t

off

turn-off time VGS= −10 to 0 V; VDD= −40 V;

− 7 − ns

ID= −200 mA

1997 Jun 18 3

Philips Semiconductors Product specification

P-channel enhancement mode
vertical D-MOS transistor

handbook, halfpage

0 V

−10 V
50 Ω

VDD = −40 V

I

D

MLD189

handbook, halfpage

INPUT

OUTPUT

10 %

t

on

90 %

90 %

t

off

BSS84

10 %

MBB690

300

handbook, halfpage

P

tot

(mW)

200

100

0

0 200

Fig.2 Switching time test circuit.

50 100 150

T

amb

MLD199

(°C)

Fig.3 Input and output waveforms.

3

−10

handbook, halfpage

I

D

(mA)

2

−10

−10

−1

−1 −10 −10

δ =0.01.

T

=25°C.

amb

(1) R

DSon

limitation.

MLD251

tp =

(1)

t

p

P

δ

t

p

T

DC

=

T

t

VDS (V)

10 µs
100 µs

1 ms

10 ms

100

ms

2

Fig.4 Power derating curve.

1997 Jun 18 4

Fig.5 DC SOAR.