Philips BSS192 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSS192
P-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of July 1993
File under Discrete Semiconductors, SC13b
1997 Jun 20
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
FEATURES
• Direct interface to C-MOS, TTL, etc.
• High-speed switching
• No secondary breakdown.
APPLICATIONS
• Line current interrupter in telephone sets
• Relay, high-speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a SOT89 package.
PINNING - SOT89
PIN SYMBOL DESCRIPTION
1 s source
2 d drain
3 g gate
handbook, halfpage
g
123
Bottom view
Marking code: KB
MAM354
Fig.1 Simplified outline and symbol.
BSS192
d
s
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MAX. UNIT
V
V
I
D
R
DS
GSth
DSon
drain-source voltage (DC) −240 V
gate-source threshold voltage ID= −1 mA; VGS=V
DS
−2.8 V
drain current (DC) −150 mA
drain-source on-state resistance ID= −100 mA; VGS= −10 V 20 Ω
1997 Jun 20 2
Philips Semiconductors Product specification
P-channel enhancement mode
BSS192
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
Note to the Limiting values and Thermal characteristics
1. Device mounted on a ceramic substrate; area 2.5 cm
drain-source voltage (DC) −−240 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) −−150 mA
peak drain current −−600 mA
total power dissipation T
≤ 25 °C; note 1 − 1W
amb
storage temperature −65 +150 °C
junction temperature − 150 °C
thermal resistance from junction to ambient note 1 125 K/W
2
; thickness 0.7 mm.
CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
y
forward transfer admittance VDS= −25 V; ID= −200 mA 60 200 − mS
fs
C
iss
C
oss
C
rss
drain-source breakdown voltage VGS= 0; ID= −10 µA −240 −−V
gate-source threshold voltage VGS=VDS; ID= −1mA −0.8 −−2.8 V
drain-source leakage current VGS= 0; VDS= −60 V −−−200 nA
= −0.2 V; VDS= −200 V −−0.1 −60 µA
V
GS
gate leakage current VDS= 0; VGS= ±20 V −−±100 nA
drain-source on-state resistance VGS= −10 V; ID= −100 mA − 10 20 Ω
input capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 55 90 pF
output capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 20 30 pF
reverse transfer capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 515pF
Switching times (see Figs 2 and 3)
t
on
turn-on time VGS=0to−10 V; VDD= −50 V;
− 510ns
ID= −250 mA
t
off
turn-off time VGS= −10 to 0 V; VDD= −50 V;
− 20 30 ns
ID= −250 mA
1997 Jun 20 3
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
handbook, halfpage
0
−10 V
50 Ω
V = −50 V
DD
I
D
MBB689
handbook, halfpage
INPUT
OUTPUT
10 %
t
on
90 %
90 %
BSS192
10 %
t
off
MBB690
1.2
handbook, halfpage
P
tot
(W)
0.8
0.4
0
0 200
Fig.2 Switching times test circuit.
MLC697
50 100 150
T ( C)
amb
Fig.3 Input and output waveforms.
160
handbook, halfpage
C
(pF)
120
80
(1)
40
0
0
o
VGS= 0; Tj=25°C; f = 1 MHz.
(1) C
iss
(2) C
oss
(3) C
rss
−5 −25
.
.
.
(2)
(3)
−10 −15 −20
MDA180
VDS (V)
Fig.4 Power derating curve.
1997 Jun 20 4
Fig.5 Capacitance as a function of drain-source
voltage; typical values.
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