Philips BSP250 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP250

P-channel enhancement mode
vertical D-MOS transistor

Product specification
Supersedes data of November 1994
File under Discrete Semiconductors, SC13b

1997 Jun 20

Philips Semiconductors Product specification

P-channel enhancement mode
vertical D-MOS transistor

FEATURES

• High-speed switching

• No secondary breakdown

• Very low on-resistance.

APPLICATIONS

• Low-loss motor and actuator drivers

• Power switching.

DESCRIPTION

P-channel enhancement mode vertical D-MOS transistor
in a SOT223 plastic SMD package.

CAUTION

The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.

PINNING - SOT223

PIN SYMBOL DESCRIPTION

1 g gate
2 d drain
3 s source
4 d drain

handbook, halfpage

123

Top view

4

g

MAM121

BSP250

d

s

Fig.1 Simplified outline and symbol.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

SD

V

GSO

V

GSth

I

D

R

DSon

P

tot

drain-source voltage (DC) −−30 V
source-drain diode forward voltage IS= −1.25 A −−1.6 V
gate-source voltage (DC) open drain −±20 V
gate-source threshold voltage ID= −1 mA; VDS=V

−1 −2.8 V

GS

drain current (DC) −−3A
drain-source on-state resistance ID= −1 A; VGS= −10 V − 0.25 Ω
total power dissipation Ts= 100 °C − 5W

1997 Jun 20 2

Philips Semiconductors Product specification

P-channel enhancement mode

BSP250

vertical D-MOS transistor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

GSO

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

Notes

1. Pulse width and duty cycle limited by maximum junction temperature.

2. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm

drain-source voltage (DC) −−30 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) Ts≤ 100 °C −−3A
peak drain current note 1 −−12 A
total power dissipation Ts= 100 °C − 5W

T

=25°C; note 2 − 1.65 W

amb

storage temperature −65 +150 °C
operating junction temperature − 150 °C

source current (DC) Ts≤ 100 °C −−1.5 A
peak pulsed source current note 1 −−6A

2

.

2.0

handbook, halfpage

P

tot

(W)

1.6

1.2

0.8

0.4

0

0 200

50 100 150

T

Fig.2 Power derating curve.

amb

MLB885

(°C)

2

−10

handbook, halfpage

I

D

(A)

−10

−1

P

−1

−10

t

p

−2

−10

−1

−10

δ =0.01.

Soldering point temperature Ts= 100 °C.
(1) R

DSon

limitation.

(1)

t

=

δ

T

t

T

−1 −10

Fig.3 SOAR.

MLB835

t

p =

10 µs

1 ms

p

DC

2

DS

(V)

−10

V

1997 Jun 20 3

Philips Semiconductors Product specification

P-channel enhancement mode

BSP250

vertical D-MOS transistor

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Note

1. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm2.

CHARACTERISTICS

=25°C unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GSth

I

DSS

I

GSS

I

Don

R

DSon

y

 forward transfer admittance VDS= −20 V; ID= −1A 1 2 − S

fs

C

iss

C

oss

C

rss

Q

G

Q

GS

Q

GD

thermal resistance from junction to ambient note 1 75 K/W
thermal resistance from junction to soldering point 10 K/W

drain-source breakdown voltage VGS= 0; ID= −10 µA −30 −−V
gate-source threshold voltage VGS=VDS; ID= −1mA −1 −−2.8 V
drain-source leakage current VGS= 0; VDS= −24 V −−−100 nA
gate leakage current VGS= ±20 V; VDS=0 −−±100 nA
on-state drain current VGS= −10 V; VDS= −1V −3 −−A

V

= −4.5 V; VDS= −5V −1 −−A

GS

drain-source on-state resistance VGS= −4.5 V; ID= −0.5 A − 0.33 0.4 Ω

V

= −10 V; ID= −1A − 0.22 0.25 Ω

GS

input capacitance VGS= 0; VDS= −20 V; f = 1 MHz − 250 − pF
output capacitance VGS= 0; VDS= −20 V; f = 1 MHz − 140 − pF
reverse transfer capacitance VGS= 0; VDS= −20 V; f = 1 MHz − 50 − pF
total gate charge VGS= −10 V; VDS= −15 V;

− 10 25 nC

ID= −2.3 A

gate-source charge VGS= −10 V; VDS= −15 V;

− 1 − nC

ID= −2.3 A

gate-drain charge VGS= −10 V; VDS= −15 V;

− 3 − nC

ID= −2.3 A

Switching times

t

on

turn-on time VGS=0to−10 V; VDD= −20 V;

ID= −1 A; RL=20Ω

t

off

turn-off time VGS= −10 to 0 V; VDD= −20 V;

ID= −1 A; RL=20Ω

Source-drain diode

V

SD

t

rr

source-drain diode forward voltage VGD= 0; IS= −1.25 A −−−1.6 V
reverse recovery time IS= −1.25 A; di/dt = 100 A/µs − 150 200 ns

1997 Jun 20 4

− 20 80 ns

− 50 140 ns