Philips BSP230 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP230

P-channel enhancement mode
vertical D-MOS transistor

Product specification
Supersedes data of 1995 Apr 07
File under Discrete Semiconductors, SC13b

1997 Jun 17

Philips Semiconductors Product specification

P-channel enhancement mode
vertical D-MOS transistor

FEATURES

• Direct interface to C-MOS, TTL, etc.

• High-speed switching

• No secondary breakdown.

APPLICATIONS

• Line current interruptor in telephone sets

• Relay, high speed and line transformer drivers.

DESCRIPTION

P-channel enhancement mode vertical D-MOS transistor
in a SOT223 plastic SMD package.

PINNING - SOT223

PIN SYMBOL DESCRIPTION

1 g gate
2 d drain
3 s source
4 d drain

BSP230

handbook, halfpage

123

Top view

Fig.1 Simplified outline and symbol.

The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.

4

d

g

s

MAM121

CAUTION

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
I

D

R
P

DS
GSO
GSth

DSon
tot

drain-source voltage (DC) −−300 V
gate-source voltage (DC) open drain −±20 V
gate-source threshold voltage ID= −1 mA; VDS=V

GS

−1.7 −2.55 V
drain current (DC) −−210 mA
drain-source on-state resistance ID= −170 mA; VGS= −10 V − 17 Ω
total power dissipation T

≤ 25 °C − 1.5 W

amb

1997 Jun 17 2

Philips Semiconductors Product specification

P-channel enhancement mode

BSP230

vertical D-MOS transistor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

GSO

I

D

I

DM

P

tot

T

stg

T

j

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

Note to the Limiting values and Thermal characteristics

1. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm

drain-source voltage (DC) −−300 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) −−210 mA
peak drain current −−0.75 A
total power dissipation T

≤ 25 °C; note 1 − 1.5 W

amb

storage temperature −65 +150 °C
operating junction temperature − 150 °C

thermal resistance from junction to ambient note 1 83.3 K/W

2

.

CHARACTERISTICS

=25°C unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GSth

I

DSS

I

GSS

R

DSon

 forward transfer admittance VDS= −25 V; ID= −170 mA 100 −−mS

y

fs

C

iss

C

oss

C

rss

drain-source breakdown voltage VGS= 0; ID= −10 µA −300 −−V
gate-source threshold voltage VDS=VGS; ID= −1mA −1.7 −−2.55 V
drain-source leakage current VGS= 0; VDS= −240 V −−−100 nA
gate leakage current VGS= ±20 V; VDS=0 −−±100 nA
drain-source on-state resistance VGS= −10 V; ID= −170 mA −−17 Ω

input capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 60 90 pF
output capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 15 30 pF
reverse transfer capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 515pF

Switching times (see Figs 2 and 3)
t

on

turn-on time VGS=0to−10 V; VDD= −50 V;

− 510ns

ID= −250 mA

t

off

turn-off time VGS= −10 to 0 V; VDD= −50 V;

− 15 30 ns

ID= −250 mA

1997 Jun 17 3

Philips Semiconductors Product specification

P-channel enhancement mode
vertical D-MOS transistor

handbook, halfpage

0

−10 V
50 Ω

V = −50 V

DD

I

D

MBB689

handbook, halfpage

INPUT

OUTPUT

10 %

t

on

90 %

90 %

BSP230

10 %

t

off

MBB690

1.6

handbook, halfpage

P

tot

(W)

1.2

0.8

0.4

0

0 200

Fig.2 Switching time test circuit.

50 100 150

T ( C)

amb

MLC687

o

Fig.3 Input and output waveforms.

handbook, halfpage

1

I

D

(A)

1

10

2

10

3

10

11010

δ = 0.01.
T

=25°C.

amb

(1) R

DSon

limitation.

MLC694

(1)

t

P

t

p

T

p

=

δ

T

t

tp =
10 µs
100 µs
1 ms
10 ms

100 ms

1 s

DC

2

V

(V)

DS

3

10

Fig.4 Power derating curve.

1997 Jun 17 4

Fig.5 DC SOAR.