Philips BSP206 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP206
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13B
April 1995
Philips Semiconductors Product specification
P-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
P-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
intended for use in relay, high-speed
and line-transformer drivers.
FEATURES
• Very low R
DS(on)
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown
QUICK REFERENCE DATA
Drain-source voltage −V
Drain current (DC) −I
Drain-source ON-resistance
−I
= 200 mA; −VGS=10V
D
Gate threshold voltage −V
PINNING - SOT223
1 = gate
2 = drain
3 = source
4 = drain
Marking code
BSP206
R
DS(on)
DS
D
GS(th)
BSP206
max. 60 V
max. 350 mA
max. 6 Ω
max. 3.5 V
PIN CONFIGURATION
handbook, halfpage
Top view
Fig.1 Simplfied outline and symbol.
4
123
MAM121
d
g
s
April 1995 2
Philips Semiconductors Product specification
P-channel enhancement mode vertical
BSP206
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage −V
Gate-source voltage (open drain) ± V
Drain current (DC) −I
Drain current (peak) −I
Total power dissipation up to T
=25°C (note 1) P
amb
Storage temperature range T
Junction temperature T
DS
GSO
D
DM
tot
stg
j
THERMAL RESISTANCE
From junction to ambient (note 1) R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min.
2
.
6cm
max. 60 V
max. 20 V
max. 350 mA
max. 700 mA
max. 1.5 W
−65 to + 150 °C
max. 150 °C
= 83.3 K/W
CHARACTERISTICS
Tj=25°C unless otherwise specified
Drain-source breakdown voltage
−I
=10µA; VGS=0
D
Drain-source leakage current
= 48 V; VGS=0
−V
DS
Gate-source leakage current
= 20 V; VDS=0
±V
GS
Gate threshold voltage
= 1 mA; VDS=V
−I
D
GS
Drain-source ON-resistance
−I
= 200 mA; −VGS=10V
D
Transfer admittance
−I
= 200 mA; −VDS=15V
D
Input capacitance at f = 1 MHz;
−V
= 10 V; VGS=0
DS
Output capacitance at f = 1 MHz;
−V
= 10 V; VGS=0
DS
Feedback capacitance at f = 1 MHz;
−V
= 10 V; VGS=0
DS
Switching times (see Figs 2 and 3)
−I
= 200 mA; −VDD=50V;
D
= 0 to 10 V t
GS
−V
(BR)DSS
−I
DSS
±I
GSS
−V
GS(th)
R
DS(on)
Yfs
C
iss
C
oss
C
rss
on
min. 60 V
max. 1.0 µA
max. 100 nA
min.
max.
typ.
max.
min.
typ.
typ.
max.
typ.
max.
typ.
max.
typ.
max.
1.5
3.5VV
4.56Ω
Ω
100
200mSmS
5570pF
pF
3045pF
pF
812pF
pF
48ns
ns−V
April 1995 3
t
off
typ.
max.
1525ns
ns
Philips Semiconductors Product specification
P-channel enhancement mode vertical
D-MOS transistor
handbook, halfpage
0 V
−10 V
50 Ω
VDD = −50 V
I
D
MBB689
handbook, halfpage
INPUT
OUTPUT
10 %
t
on
90 %
90 %
BSP206
10 %
t
off
MBB690
handbook, halfpage
I
D
(mA)
−10
−10
VGS = −10 V
2
3
−10
Fig.2 Switching time test circuit.
−7.5 V
−6 V
−5 V
−4.5 V
10 12 14
R
DSon
MDA756
(Ω)
Fig.3 Input and output waveforms.
−8
VGS (V)
MDA757
−1
handbook, halfpage
I
D
(A)
−0.8
−0.6
−0.4
−0.2
164 86
0
0 −10
−2 −4 −6
Fig.4 ON-resistance as a function of drain
current; Tj=25°C; typical values.
April 1995 4
Fig.5 Transfer characteristics; −VDS=10V;
Tj=25°C; typical values.
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