Philips BSP152 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP152
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown.
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
SOT223 envelope, intended for use
as a line current interruptor in
telephone sets and for applications in
relay, high-speed and line
transformer drivers.
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
drain-source
voltage
I
D
P
tot
DC drain current − 550 mA
total power
dissipation
±V
GSO
gate-source
voltage
R
DS(on)
drain-source
on-resistance
V
GS(off)
gate-source
cut-off voltage
handbook, halfpage
123
Top view
BSP152
− 200 V
up to T
open drain − 40 V
ID = 750 mA;
VGS = 10 V
ID = 1 mA;
VDS = V
4
= 25 °C − 1.5 W
amb
− 2.5 Ω
1.5 3.5 V
GS
d
g
s
MAM054
April 1995 2
Fig.1 Simplified outline and symbol.
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP152
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
±V
GSO
I
D
I
DM
P
tot
T
stg
T
j
THERMAL RESISTANCE
SYMBOL PARAMETER THERMAL RESISTANCE
R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 mm
drain-source voltage − 200 V
gate-source voltage open drain − 40 V
DC drain current − 550 mA
peak drain current − 3A
total power dissipation up to T
= 25 °C; note 1 − 1.5 W
amb
storage temperature −65 +150 °C
operating junction temperature − 150 °C
from junction to ambient; note 1 83.3 K/W
2
.
STATIC CHARACTERISTICS
= 25 °C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
±I
GSS
V
GS(th)
R
DS(on)
I
DSS
| transfer admittance ID = 750 mA; VDS = 25 V 400 −−mS
| Y
fs
C
iss
drain-source breakdown voltage ID = 10 µA; VGS = 0 200 −−V
gate-source leakage current ±VGS = 40 V; VDS = 0 −−100 nA
gate-source threshold voltage ID = 1 mA; VDS = V
GS
1.5 − 3.5 V
drain-source on-resistance ID = 750 mA; VGS = 10 V −−2.5 Ω
drain-source leakage current VDS = 160 V; VGS = 0 −−100 nA
input capacitance VDS = 25 V; VGS = 0;
− 100 − pF
f = 1 MHz
C
oss
C
rss
output capacitance VDS = 25 V; VGS = 0; f = 1 MHz − 42 − pF
feedback capacitance VDS = 25 V; VGS = 0; f = 1 MHz − 8 − pF
Switching times (see Figs 2 and 3)
t
on
turn-on time ID = 750 mA; VDD = 50 V;
−−15 ns
VGS = 0 to 10 V
t
off
turn-off time ID = 750 mA; VDD = 50 V;
−−30 ns
VGS = 10 to 0 V
April 1995 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
handbook, halfpage
10 V
0 V
50 Ω
VDD = 50 V
I
D
MSA631
handbook, halfpage
INPUT
OUTPUT
10 %
t
on
90 %
90 %
BSP152
10 %
t
off
MBB692
handbook, halfpage
2
P
tot
(W)
1.5
1
0.5
0
0 50 100 150
Fig.2 Switching times test circuit.
MRC207
T
(°C)
amb
Fig.3 Input and output waveforms.
300
handbook, halfpage
C
(pF)
200
100
0
0102030
VGS = 0; f = 1 MHz;Tj = 25 °C.
MRC203
VDS (V)
C
iss
C
oss
C
rss
Fig.4 Power derating curve.
April 1995 4
Fig.5 Capacitance as a function of drain-source
voltage, typical values.
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