Philips BSP130 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP130

N-channel enhancement mode
vertical D-MOS transistor

Product specification
File under Discrete Semiconductors, SC13b

April 1995

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

FEATURES

• Direct interface to C-MOS, TTL,
etc.

• High-speed switching

• No secondary breakdown.

DESCRIPTION

N-channel enhancement mode
vertical D-MOS transistor in a
SOT223 envelope, intended for use
as a line current interruptor in
telephone sets and for applications in
relay, high-speed and line
transformer drivers.

PINNING - SOT223

PIN DESCRIPTION

1 gate
2 drain
3 source
4 drain

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

drain-source
voltage

I

D

P

tot

DC drain current − 300 mA
total power

dissipation
±V
R

DS(on)

GSO

gate-source voltage open drain − 20 V

drain-source

on-resistance
V

GS(off)

gate-source cut-off

voltage

handbook, halfpage

123

Top view

up to T

amb

ID = 250 mA;

= 10 V

V

GS

ID = 1 mA;
VDS = V

4

GS

g

MAM054

BSP130

− 300 V

= 25 °C − 1.5 W

− 8 Ω

0.8 2 V

d

s

Marking code

BSP130.

April 1995 2

Fig.1 Simplified outline and symbol.

Philips Semiconductors Product specification

N-channel enhancement mode vertical

BSP130

D-MOS transistor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

±V

GSO

I

D

I

DM

P

tot

T

stg

T

j

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

R

th j-a

Note

1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm

drain-source voltage − 300 V
gate-source voltage open drain − 20 V
DC drain current − 300 mA
peak drain current − 1.4 A
total power dissipation up to T

= 25 °C; note 1 − 1.5 W

amb

storage temperature −65 +150 °C
junction temperature − 150 °C

from junction to ambient; note 1 83.3 K/W

2

.

STATIC CHARACTERISTICS

= 25 °C unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

±I

GSS

V

GS(th)

R

DS(on)

I

DSS

 Y

 transfer admittance ID = 250 mA; VDS = 25 V 200 380 − mS

fs

C

iss

drain-source breakdown voltage ID = 10 µA; VGS = 0 300 −−V
gate-source leakage current ±VGS = 20 V; VDS = 0 −−100 nA
gate-source threshold voltage ID = 1 mA; VDS = V

GS

0.8 − 2V

drain-source on-resistance ID = 20 mA; VGS = 2.4 V − 7.9 14 Ω

I

= 250 mA; VGS = 10 V − 6.7 8 Ω

D

drain-source leakage current VDS = 240 V; VGS = 0 −−100 nA

input capacitance VDS = 25 V; VGS = 0;

− 57 90 pF

f = 1 MHz

C

oss

output capacitance VDS = 25 V; VGS = 0;

− 15 30 pF

f = 1 MHz

C

rss

feedback capacitance VDS = 25 V; VGS = 0;

− 2.6 15 pF

f = 1 MHz
Switching times (see Figs 2 and 3)
t

on

turn-on time ID = 250 mA; VDD = 50 V;

− 2.5 10 ns

VGS= 0 to 10 V
t

off

turn-off time ID = 250 mA; VDD = 50 V;

− 17 30 ns

VGS= 10 to 0 V

April 1995 3

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

handbook, halfpage

10 V

0 V

50 Ω

VDD = 50 V

I

D

MBB691

handbook, halfpage

INPUT

OUTPUT

10 %

t

on

90 %

90 %

BSP130

10 %

t

off

MBB692

handbook, halfpage

2

P

tot

(W)

1.5

1

0.5

0

0 50 100

Fig.2 Switching times test circuit.

MRC218

150

Tj (°C)

200

Fig.3 Input and output waveforms.

150

handbook, halfpage

C

(pF)

100

50

0

0

VGS= 0; f= 1MHz; Tj=25°C.

525

C

C
C

10 15 20

MRC214

iss

oss
rss

VDS (V)

Fig.4 Power derating curve.

April 1995 4

Fig.5 Capacitance as a function of drain-source

voltage, typical values.