Philips BSP126 Datasheet

DISCRETE SEMICONDUCTORS

DATA SH EET

BSP126

N-channel enhancement mode
vertical D-MOS transistor

Product specification
File under Discrete Semiconductors, SC13b

April 1995

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

DESCRIPTION

N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
designed for use as a line interrupter
in telephone sets and for application
in relay, high-speed and
line-transformer drivers.

FEATURES

• Direct interface to C-MOS, TTL,
etc.

• High-speed switching.

• No secondary breakdown.

QUICK REFERENCE DATA

Drain-source voltage V
Drain current (DC) I
Total power dissipation up to T
Drain-source on-resistance

ID= 300 mA; VGS= 10 V R

Gate-source threshold voltage V

PINNING - SOT223

1 = gate
2 = drain
3 = source
4 = drain

Marking code

=25°CP

amb

DS

D

tot

DS(on)

GS(th)

BSP126

max. 250 V
max. 350 mA
max. 1.5 W

typ.
max.

max. 2 V

5.0

7.0ΩΩ

PIN CONFIGURATION

BSP126

handbook, halfpage

Top view

Fig.1 Simplified outline and symbol.

4

123

MAM054

d

g

s

April 1995 2

Philips Semiconductors Product specification

N-channel enhancement mode vertical

BSP126

D-MOS transistor

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Drain-source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T

=25°C (note 1) P

amb

Storage temperature range T
Junction temperature T

DS

GSO
D
DM

tot
stg
j

THERMAL RESISTANCE

From junction to ambient (note 1) R

th j-a

Note

1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead
min. 6 cm

2

.

max. 250 V
max. 20 V
max. 350 mA
max. 1.2 A
max. 1.5 W

−65 to + 150 °C

max. 150 °C

= 83.3 K/W

CHARACTERISTICS

=25°C unless otherwise specified

T

j

Drain-source breakdown voltage

I

=10µA; VGS=0 V

D

Drain-source leakage current

VDS= 200 V; VGS=0 I

Gate-source leakage current

± V

= 20 V; VDS=0 ±I

GS

Gate threshold voltage

ID= 1 mA; VDS= V

GS

Drain-source on-resistance

= 300 mA; VGS= 10 V R

I

D

ID= 20 mA; VGS= 2.4 V R

Transfer admittance

I

= 300 mA; VDS= 25 V  Yfs

D

Input capacitance at f = 1 MHz;

= 25 V; VGS=0 C

V

DS

(BR)DSS

DSS

GSS

V

GS(th)

DS(on)

DS(on)

iss

min. 250 V

max. 1.0 µA

max. 100 nA

min.
max.

typ.
max.

0.8

2.0VV

5.0

7.0ΩΩ

max. 10 Ω

min.
typ.

typ.
max.

200
400mSmS

6590pF

pF

Output capacitance at f = 1 MHz;

= 25 V; VGS=0 C

V

DS

April 1995 3

oss

typ.
max.

2030pF

pF

Philips Semiconductors Product specification

N-channel enhancement mode vertical
D-MOS transistor

Feedback capacitance at f = 1 MHz;

= 25 V; VGS=0 C

V

DS

Switching times (see Figs 2 and 3)

I

= 250 mA; VDD= 50 V;

D

VGS= 0 to 10 V t

handbook, halfpage

VDD = 50 V

handbook, halfpage

INPUT

BSP126

rss

on

t

off

typ.
max.

typ.
max.

typ.
max.

90 %

515pF

pF

510ns

ns

2030ns

ns

10 V

0 V

50 Ω

I

D

MSA631

Fig.2 Switching time test circuit.

10 %

90 %

OUTPUT

t

on

Fig.3 Input and output waveforms.

10 %

t

off

MBB692

April 1995 4